JAJSDX2C September   2017  – October 2021 LM5150-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable (EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 8.3.3  Power-On Voltage Selection (VSET Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 8.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 8.3.7  Current Limit (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 8.3.9  Automatic Wake-Up and Standby
      10. 8.3.10 Boost Status Indicator (STATUS Pin)
      11. 8.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (LO Pin)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Wake-Up Mode
        1. 8.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 8.4.3.2 Emergency-Call Configuration (EC Configuration)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bypass Switch / Disconnection Switch Control
      2. 9.1.2 Loop Response
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  RSET Resistor
        3. 9.2.2.3  RT Resistor
        4. 9.2.2.4  Inductor Selection (LM)
        5. 9.2.2.5  Current Sense (RS)
        6. 9.2.2.6  Slope Compensation Ramp (RSL)
        7. 9.2.2.7  Output Capacitor (COUT)
        8. 9.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 9.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 9.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 9.2.2.11 Input Capacitor
        12. 9.2.2.12 MOSFET Selection
        13. 9.2.2.13 Diode Selection
        14. 9.2.2.14 Efficiency Estimation
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Lower Standby Threshold in SS Configuration
      2. 9.3.2 Dithering Using Dither Enabled Device
      3. 9.3.3 Clock Synchronization With LM5140
      4. 9.3.4 Dynamic Frequency Change
      5. 9.3.5 Dithering Using an External Clock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

8.3.9 Automatic Wake-Up and Standby

The LM5150-Q1 wakes up when VVOUT drops below the VOUT wake-up threshold. The device goes into standby when VVOUT rises above the VOUT standby threshold in EC or SS configuration or when VVIN rises above the VIN standby threshold in SS configuration. The VOUT wake-up threshold is typically 3% higher than the VOUT regulation target. The STATUS output is released in 3 µs (with a 50-kΩ pullup resistor to 5 V) after the wake-up event. The LO driver is enabled 6 µs after the STATUS output starts rising.

GUID-C1DCA251-0211-4BE1-AE28-4BFCAC46609E-low.gifFigure 8-3 Automatic Wake-Up and Standby Control

In SS configuration, the VOUT standby threshold is typically 24% higher than the VOUT regulation target. The VIN standby threshold is typically 1 V higher than the VOUT wake-up threshold in SS configuration. To prevent chatter, the forward voltage drop of diode D1 must be less than 0.95 V. See Figure 8-7.

GUID-0068E67A-6156-4D8A-8499-16417F5D88D1-low.gifFigure 8-4 Automatic Wake-Up and Standby Operation in the SS Configuration (With Fast VSUPPLY Fall and Slow Switching)
GUID-F5638EA5-F784-444A-A6F1-404ABCF50DCA-low.gifFigure 8-5 Automatic Wake-Up and Standby Operation in the SS Configuration (With Slow VSUPPLY Fall and Fast Switching)

In EC configuration, the VOUT standby threshold is typically 6% higher than the VOUT regulation target. Because of the minimum duty cycle limit (see Section 8.4.3.2), the LM5150-Q1 alternates between the wake-up and the low IQ standby modes at medium or light load. See Figure 8-8.

GUID-AF1C582A-1FA2-4845-B56D-3394F0D2C702-low.gifFigure 8-6 Automatic Wake-Up and Standby Operation in EC Configuration

To minimize output undershoot when waking up, the LM5150-Q1 boosts the VOUT regulation target during the first 128 cycles after the wake-up event. The regulation target becomes 3% higher than the original regulation target for 64 cycles, 2% higher for the next 32 cycles and 1% higher for the final 32 cycles. The VOUT pin voltage can rise up above the VOUT standby threshold even if switching stops at the VOUT standby threshold because the energy stored in the inductor transfers to the output capacitor when switching stops. See Section 8.4 for more information about the automatic wake-up and standby operation.