JAJSDX2C September 2017 – October 2021 LM5150-Q1
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When designing a boost converter, the maximum duty cycle should be reviewed at the minimum supply voltage. The minimum input supply voltage which can achieve the target output voltage is estimated from Equation 9.
where
Substitute FSW_RT for FSYNC if the clock synchronization is not used. The minimum input supply voltage can be decreased by supplying FSYNC which is less than FSW_RT.
This maximum duty cycle limit (DMAX) is 87% (typical), but can fall down below 80% if the external synchronization clock frequency is higher than 0.85 × FSW (TYPICAL). Select an FSYNC which is within –25% and –15% of the FSW (TYPICAL) if 1:5 step-up ratio is required with clock synchronization. The minimum input supply voltage can be further decreased by supplying a lower frequency external synchronization clock. See Section 8.3.5 for more information.