JAJSDX2C September   2017  – October 2021 LM5150-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable (EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 8.3.3  Power-On Voltage Selection (VSET Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 8.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 8.3.7  Current Limit (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 8.3.9  Automatic Wake-Up and Standby
      10. 8.3.10 Boost Status Indicator (STATUS Pin)
      11. 8.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (LO Pin)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Wake-Up Mode
        1. 8.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 8.4.3.2 Emergency-Call Configuration (EC Configuration)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bypass Switch / Disconnection Switch Control
      2. 9.1.2 Loop Response
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  RSET Resistor
        3. 9.2.2.3  RT Resistor
        4. 9.2.2.4  Inductor Selection (LM)
        5. 9.2.2.5  Current Sense (RS)
        6. 9.2.2.6  Slope Compensation Ramp (RSL)
        7. 9.2.2.7  Output Capacitor (COUT)
        8. 9.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 9.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 9.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 9.2.2.11 Input Capacitor
        12. 9.2.2.12 MOSFET Selection
        13. 9.2.2.13 Diode Selection
        14. 9.2.2.14 Efficiency Estimation
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Lower Standby Threshold in SS Configuration
      2. 9.3.2 Dithering Using Dither Enabled Device
      3. 9.3.3 Clock Synchronization With LM5140
      4. 9.3.4 Dynamic Frequency Change
      5. 9.3.5 Dithering Using an External Clock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RUM|16
サーマルパッド・メカニカル・データ
発注情報

9.1.2 Loop Response

The open-loop transfer function of a boost regulator is defined as the product of modulator transfer function and feedback transfer function.

The modulator transfer function of a current mode boost regulator including a power stage with an embedded current loop can be simplified as a one load pole (FLP), one ESR zero (FZ_ESR), and one Right Half Plane (RHP) zero (FRHP) system, which can be explained as follows.

Modulator transfer function is defined as follows:

Equation 15. GUID-CD14B436-9946-49A4-8A40-4E9953A1D66B-low.gif

where

  • GUID-B7D012FE-1497-4A71-9DA9-33FC54FF3152-low.gif
  • GUID-D82286D9-1C50-42EA-A53D-6D848C28E741-low.gif
  • GUID-D23AF270-F870-4021-82C3-4ADED9D5E255-low.gif
  • GUID-9231ED92-DE6F-4FC8-9C36-3F305F2C0198-low.gif

RESR is the equivalent series resistance (ESR) of the output capacitor which is specified in the capacitor data sheet.

RCOMP, CCOMP, and CHF (see Figure 9-3) configure the error amplifier gain and phase characteristics to produce a stable voltage loop with fast response. This compensation network creates a dominant pole at low frequency (FDP_EA), a mid-band zero (FZ_EA), and a high frequency pole (FP_EA).

The feedback transfer function is defined as follows:

Equation 16. GUID-3CA0DC8B-93E0-4E80-8D78-B3F1235BC4B2-low.gif

where

  • GUID-65F01283-4157-402F-BD01-95BEF815AE61-low.gif
  • GUID-A9B7FF42-CFB5-452F-914F-D16A8819A77F-low.gif
  • GUID-7C31C6CE-6EF2-4B90-A197-18BC04F11EEF-low.gif
  • GUID-F6252652-6BB4-421B-9A31-52AA7772A03F-low.gif

RO (≈ 10 MΩ) is the output resistance of the error amplifier and Gm (≈ 2 mA/V) is the transconductance of the error amplifier.

Assuming FLP is canceled by FZ_EA, FRHP is much higher than crossover frequency (FCROSS), and FZ_ESR is either canceled by FP_EA or FZ_ESR is much higher than FCROSS, the open-loop transfer function can be simplified as follows:

Equation 17. GUID-02B5037C-AAEC-484B-9353-F999B8FC8C70-low.gif

Because |T(s)| = 1 at the crossover frequency, the crossover frequency can be simply estimated using those assumptions.

Equation 18. GUID-D215B883-BD5E-4DC0-BC8A-EA9598EC044A-low.gif