JAJSDX2C September   2017  – October 2021 LM5150-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable (EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 8.3.3  Power-On Voltage Selection (VSET Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 8.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 8.3.7  Current Limit (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 8.3.9  Automatic Wake-Up and Standby
      10. 8.3.10 Boost Status Indicator (STATUS Pin)
      11. 8.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (LO Pin)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Wake-Up Mode
        1. 8.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 8.4.3.2 Emergency-Call Configuration (EC Configuration)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bypass Switch / Disconnection Switch Control
      2. 9.1.2 Loop Response
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  RSET Resistor
        3. 9.2.2.3  RT Resistor
        4. 9.2.2.4  Inductor Selection (LM)
        5. 9.2.2.5  Current Sense (RS)
        6. 9.2.2.6  Slope Compensation Ramp (RSL)
        7. 9.2.2.7  Output Capacitor (COUT)
        8. 9.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 9.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 9.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 9.2.2.11 Input Capacitor
        12. 9.2.2.12 MOSFET Selection
        13. 9.2.2.13 Diode Selection
        14. 9.2.2.14 Efficiency Estimation
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Lower Standby Threshold in SS Configuration
      2. 9.3.2 Dithering Using Dither Enabled Device
      3. 9.3.3 Clock Synchronization With LM5140
      4. 9.3.4 Dynamic Frequency Change
      5. 9.3.5 Dithering Using an External Clock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

9.2.2.7 Output Capacitor (COUT)

There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be selected based on output voltage ripple, output overshoot, or undershoot due to load transient. In this example, COUT is selected based on output undershoot because the waking up performance is similar with no-load to full-load transient performance.

The output undershoot becomes smaller by increasing FCROSS or by decreasing FLP: a smaller COUT is allowed by increasing FCROSS or by decreasing FLP.

To increase FCROSS, FSW, and FRHP must be increased because the maximum FCROSS is, in general, limited at 1/10 of FRHP at VSUPPLY(MIN) or 1/10 of FSW whichever is lower.

FRHP is calculated using Equation 28.

Equation 28. GUID-636275E2-1D3A-4667-BDDE-D823C80450B1-low.gif

FCROSS is selected at 1/10 of FRHP or 1/10 of FSW, whichever is lower.

Equation 29. GUID-DB09F38A-255F-4982-A823-CCE6212E9964-low.gif
Equation 30. GUID-0557F9B3-37AB-46A1-9933-5588175F140B-low.gif

In this example, 2.27 kHz is selected as a target FCROSS and FLP is selected to be 340 Hz (K1 = 0.15).

In general, there is about 5% or less undershoot with FLP = 0.1 × FCROSS (K1 = 0.1) and 10% or less undershoot with FLP = 0.2 × FCROSS (K1 = 0.2) during 0% to 100% load transient. The recommended K1 factor range is from 0.02 to 0.2.

FLP is calculated using Equation 31.

Equation 31. GUID-7471297A-0CC5-45B3-824B-19161143B0CD-low.gif

The minimum required output capacitance value is calculated using Equation 32.

Equation 32. GUID-5CEE1153-8C10-4EC3-8673-599443E95517-low.gif

The maximum output ripple current is calculated at the minimum input supply voltage as follows:

Equation 33. GUID-3E5A4211-8AD3-418B-87CC-06E0C9620337-low.gif

The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the diode and the MOSFET than the bulk aluminum capacitors to absorb the majority of the ripple current.

In this example, three 100-µF capacitors are placed in parallel to ensure ripple current capability. If high-ESR capacitors are used for the output capacitor, additional 10-µF ceramic capacitors can be placed close to the switching components to minimize switching noise.