JAJSDX2C September   2017  – October 2021 LM5150-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable (EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 8.3.3  Power-On Voltage Selection (VSET Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 8.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 8.3.7  Current Limit (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 8.3.9  Automatic Wake-Up and Standby
      10. 8.3.10 Boost Status Indicator (STATUS Pin)
      11. 8.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (LO Pin)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Wake-Up Mode
        1. 8.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 8.4.3.2 Emergency-Call Configuration (EC Configuration)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bypass Switch / Disconnection Switch Control
      2. 9.1.2 Loop Response
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  RSET Resistor
        3. 9.2.2.3  RT Resistor
        4. 9.2.2.4  Inductor Selection (LM)
        5. 9.2.2.5  Current Sense (RS)
        6. 9.2.2.6  Slope Compensation Ramp (RSL)
        7. 9.2.2.7  Output Capacitor (COUT)
        8. 9.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 9.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 9.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 9.2.2.11 Input Capacitor
        12. 9.2.2.12 MOSFET Selection
        13. 9.2.2.13 Diode Selection
        14. 9.2.2.14 Efficiency Estimation
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Lower Standby Threshold in SS Configuration
      2. 9.3.2 Dithering Using Dither Enabled Device
      3. 9.3.3 Clock Synchronization With LM5140
      4. 9.3.4 Dynamic Frequency Change
      5. 9.3.5 Dithering Using an External Clock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

8.4.3.2 Emergency-Call Configuration (EC Configuration)

GUID-31496AD0-6C6E-431F-9AD3-70AF27487327-low.gifFigure 8-8 Typical Emergency Call Application

The EC configuration achieves high efficiency at light/medium load by alternating between the wake-up and low IQ standby modes. In EC configuration, the LM5150-Q1 limits the minimum duty cycle programmed by VVOUT and VVIN. The minimum duty cycle limit is calculated using Equation 12.

Equation 12. GUID-D6AA7527-9D32-45BB-AD4E-503CABB00E9D-low.gif

Due to this minimum duty cycle limit, the boost converter sources more current than required when the load current is relatively small. As a result, the output voltage increases and eventually crosses the VOUT standby threshold which is typically 6% higher than the VOUT regulation target. The LM5150-Q1 then goes into the low IQ standby mode. The LM5150-Q1 wakes up when VOUT drops below the VOUT wake-up threshold which is typically 3% higher than the VOUT regulation target. The device alternates between these two modes when the inequality below is true.

Equation 13. GUID-E672ADA9-875D-4015-AC36-48761D2A9712-low.gif

Assuming VLOAD = VVOUT = VVOUT-REG and VSUPPLY = VVIN, the skip cycle operation starts when the inequality below is true.

Equation 14. GUID-ACCAFE27-EF43-429D-98B6-41AC8A33E921-low.gif

In EC configuration, the LM5150-Q1 does not generate any pulse if VCOMP is less than the 0.3 V and the required minimum duty cycle limit is zero.

If the peak current limit is triggered before reaching the minimum duty cycle, the device terminates the LO driver output immediately.

If VOUT is greater than the VOUT status-off threshold (typically 12% higher than the VOUT regulation target), the LM5150-Q1 pulls the STATUS pin low.

In EC configuration, light load efficiency is proportional with the inductor current ripple ratio.

Table 8-4 State of Each Pin in Wake-Up Mode
STATUSSYNCRTCOMPENVOUTPVCC/AVCCLOCSVINVSET
ReleasedEnabled in SS configurationEnabledEnabledEnabledVOUT standby monitor is enabled. VOUT status-off monitor is enabled in EC configuration.Enabled IPVCC capability ≈ 75 mAPWMEnabledIQ ≈ 30 µA. VIN status-off monitor is enabled in SS configurationDisabled
Table 8-5 Start-Stop versus Emergency-Call Configuration
CONFIGURATIONSTART-STOPEMERGENCY-CALL
VOUT regulation options6.8 V, 7.5 V, 8.5 V, 10.5 V
VSET resistor value [Ω]29.4 k, 19.1 k, 9.53 k, GND90.9 k, 71.5 k, 54.9 k, 41.2 k
Clock SynchronizationYesNo, SYNC should be grounded
VOUT wake-up threshold [V]VVOUT-REG × 1.03
VOUT standby threshold [V]VVOUT-REG × 1.24VVOUT-REG × 1.06
VOUT status-off threshold [V]N/AVVOUT-REG × 1.12
VIN standby threshold [V]VVOUT-REG × 1.03 + 1.0 VN/A
STATUS pin control (Open-drain with pullup resistor)Released by VOUT wake-up
Pulled down by VIN standby		Released by VOUT wake-up
Pulled down by VOUT status-off
At heavy load when VVIN « VVOUTPulse width modulation (PWM)
At light/no load when VVIN « VVOUTLO turns on at every cycle in wake-up configuration. Skip cycle operation by alternating between wake-up and standby configurations.
Minimum on-time is limitedMinimum duty cycle is limited
When VVIN ≈ VVOUT or VVIN ≥ VVOUTLO turns on at every cycle in wake-up configuration. On-time is limited by TON-MIN. VOUT goes out of regulation.Duty cycle can drop to 0%. No pulses if VCOMP < 0.3 V and DMIN ≤ 0%.
Maximum duty-cycle limitTypically 87%