JAJSDX2C September 2017 – October 2021 LM5150-Q1
PRODUCTION DATA
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In SS configuration, the switching frequency of the LM5150-Q1 can be synchronized to an external clock by directly applying a pulse signal to the SYNC pin. The internal clock of the LM5150-Q1 is synchronized at the rising edge of the external clock. The device ignores the rising edge input during forced off-time.
The external synchronization pulse must be greater than the 2.4 V in the high logic state and must be less than 0.4 V in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum pulse width should be greater than 100 ns. Because the maximum duty cycle limit and the peak current limit threshold are affected by synchronizing the switching frequency to an external synchronization pulse, take extra care when using the clock synchronization function. See Section 8.3.11 and Section 8.3.7 for more detailed information.
If the minimum input supply voltage of the boost converter is greater than ¼ of the VOUT regulation target (VVOUT-REG), the frequency of the external synchronization pulse (FSYNC) should be within +15% and –15% of the typical free-running switching frequency (FSW(TYPICAL))
In this range, a maximum 1:4 (VSUPPLY:VLOAD) step-up ratio is allowed.
A higher step-up ratio can be achieved by supplying a lower frequency synchronization pulse. 1:5 step-up ratio can be achieved by selecting FSYNC within –25% and –15% of the FSW_RT(TYPICAL).
In this range, a maximum 1:5 (VSUPPLY:VLOAD) step-up ratio is allowed.