JAJSNZ8A February   2022  – April 2022 LM5152-Q1 , LM51521-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Enable/Disable (EN, VH Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 9.3.4  Line Undervoltage Lockout (UVLO Pin)
      5. 9.3.5  Fast Restart Using VCC HOLD (VH Pin)
      6. 9.3.6  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      7. 9.3.7  Overvoltage Protection (VOUT Pin)
      8. 9.3.8  Boost Status Indicator (STATUS Pin)
      9. 9.3.9  Dynamically Programmable Switching Frequency (RT)
      10. 9.3.10 External Clock Synchronization (SYNC Pin)
      11. 9.3.11 Programmable Spread Spectrum (DITHER Pin)
      12. 9.3.12 Programmable Soft Start (SS Pin)
      13. 9.3.13 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      14. 9.3.14 Current Sensing and Slope Compensation (CSP, CSN Pin)
      15. 9.3.15 Constant Peak Current Limit (CSP, CSN Pin)
      16. 9.3.16 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      17. 9.3.17 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      18. 9.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 9.3.19 Thermal Shutdown Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Status
        1. 9.4.1.1 Shutdown Mode
        2. 9.4.1.2 Configuration Mode
        3. 9.4.1.3 Active Mode
        4. 9.4.1.4 Sleep Mode
        5. 9.4.1.5 Deep Sleep Mode
      2. 9.4.2 Light Load Switching Mode
        1. 9.4.2.1 Forced PWM (FPWM) Mode
        2. 9.4.2.2 Diode Emulation (DE) Mode
        3. 9.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 9.4.2.4 Skip Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application Ideas
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.11 Programmable Spread Spectrum (DITHER Pin)

The device provides an optional programmable spread spectrum (clock dithering) function that is activated by connecting a capacitor between DITHER and AGND. A triangular waveform centered at 1.0 V is generated across the dither capacitor. This triangular waveform modulates the oscillator frequency by –6% to +5% of the frequency set by the RT resistor. The dither capacitance value sets the rate of the low frequency modulation.

GUID-20200812-CA0I-5V0S-TWTW-6DSFJ2RH3WNH-low.gif Figure 9-10 Switching Frequency Dithering

For the dithering circuit to effectively reduce peak EMI, the modulation frequency must be much less than the RT switching frequency. The dither capacitance, which is required for a given modulation frequency (fMOD), can be calculated from Equation 8. Setting the fMOD to 9 kHz or 10 kHz is a good starting point.

Equation 8. C D I T H E R = 20 μ A f M O D × 0 . 29

Connecting DITHER to AGND deactivates clock dithering, and the internal oscillator operates at a fixed frequency set by the RT resistor. Clock dithering is also disabled when an external synchronization pulse is applied.

GUID-20200812-CA0I-15FV-1XSL-KNSRRQSTWQJV-low.gif Figure 9-11 Dynamic Dither On/Off Example

Connecting STATUS to DITHER enables the clock dithering when the STATUS pin is pulled down to ground and also enables the internal charge pump during bypass operation when the STATUS pin is pulled up.

GUID-20210514-CA0I-8PZN-PNVV-BJFM2MQ3PNZB-low.gif Figure 9-12 Enable Clock Dithering and Internal Charge Pump Together