JAJSMA8A july   2021  – august 2023 LM5157

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 8.3.3  Soft Start (SS Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Dual Random Spread Spectrum – DRSS (MODE Pin)
      6. 8.3.6  Clock Synchronization (UVLO/SYNC/EN Pin)
      7. 8.3.7  Current Sense and Slope Compensation
      8. 8.3.8  Current Limit and Minimum On Time
      9. 8.3.9  Feedback and Error Amplifier (FB, COMP Pin)
      10. 8.3.10 Power-Good Indicator (PGOOD Pin)
      11. 8.3.11 Hiccup Mode Overload Protection (MODE Pin)
      12. 8.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      13. 8.3.13 Internal MOSFET (SW Pin)
      14. 8.3.14 Overvoltage Protection (OVP)
      15. 8.3.15 Thermal Shutdown (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
        1. 8.4.3.1 Spread Spectrum Enabled
        2. 8.4.3.2 Hiccup Mode Protection Enabled
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Recommended Components
        3. 9.2.2.3 Inductor Selection (LM)
        4. 9.2.2.4 Output Capacitor (COUT)
        5. 9.2.2.5 Input Capacitor
        6. 9.2.2.6 Diode Selection
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
      3. 12.1.3 Export Control Notice
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS) BIAS shutdown current VBIAS = 12 V, VUVLO = 0 V 2.6 5 μA
IOPERATING(BIAS) BIAS operating current VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ 700 850 μA
VCC REGULATOR
VVCC-REG VCC regulation VBIAS = 8 V, IVCC = 18 mA 4.66 4.9 5.14 V
VVCC-UVLO(RISING) VCC UVLO threshold VCC rising 2.75 2.8 2.85 V
VCC UVLO hysteresis VCC falling 0.1 V
ENABLE
VEN(RISING) Enable threshold EN rising 0.4 0.52 0.7 V
VEN(FALLING) Enable threshold EN falling 0.33 0.49 0.63 V
VEN(HYS) Enable hysteresis EN falling 0.03 V
UVLO/SYNC
VUVLO(RISING) UVLO / SYNC threshold UVLO rising 1.425 1.5 1.575 V
VUVLO(FALLING) UVLO / SYNC threshold UVLO falling 1.370 1.45 1.520 V
VUVLO(HYS) UVLO / SYNC threshold hysteresis UVLO falling 0.05 V
IUVLO UVLO hysteresis current VUVLO = 1.6 V 4 5 6 μA
MODE, SPREAD SPECTRUM
FSW modulation (upper limit) 7.8%
FSW modulation (lower limit) –7.8%
SS
ISS Soft-start current 9 10 11 μA
SS pulldown switch RDSON 50 Ω
PULSE WIDTH MODULATION
fsw1 Switching frequency RT = 220 kΩ 85 100 115 kHz
fsw2 Switching frequency RT = 49.3 kΩ 388 440 492 kHz
fsw3 Switching frequency RT = 9.09 kΩ 1980 2200 2420 kHz
tON(MIN) Minimum on time RT = 9.09 kΩ 80 ns
DMAX1 Maximum duty cycle limit RT = 9.09 kΩ 80% 85% 90%
DMAX2 Maximum duty cycle limit RT = 220 kΩ 90% 93% 96%
RT regulation voltage 0.5 V
CURRENT LIMIT
ILIM Internal MOSFET current limit LM5157 6.5 7.5 8.5 A
Internal MOSFET current limit LM51571 4.33 5 5.67 A
HICCUP MODE PROTECTION
Hiccup enable cycles 64 Cycles
Hiccup timer reset cycles 8 Cycles
ERROR AMPLIFIER
VREF FB reference 0.99 1 1.01 V
Gm Transconductance 2 mA/V
COMP sourcing current VCOMP = 1.2 V 180 μA
COMP clamp voltage COMP rising (VUVLO = 2.0 V) 2.5 2.8 V
COMP clamp voltage COMP falling 1 1.1 V
ACS  ΔVCOMP / ΔISW 0.095
OVP
VOVTH Overvoltage threshold FB rising (referece to VREF) 107% 110% 113%
Overvoltage threshold FB falling (referece to VREF) 105%
PGOOD
PGOOD pulldown switch RDSON 1 mA sinking 70 Ω
VUVTH Undervoltage threshold FB falling (referece to VREF) 87% 90% 93%
Undervoltage threshold FB rising (referece to VREF) 95%
POWER SWITCH
rDS(ON) Internal MOSFET on-resistance VBIAS = 12 V 45 90 mΩ
VBIAS = 3.5 V 47 95 mΩ
Leakage current VSW = 12 V 1200 nA
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold Temperature rising 175 °C
Thermal shutdown hysteresis 15 °C