JAJSGD5E
October 2014 – October 2018
LM5160
,
LM5160A
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
代表的な同期整流降圧アプリケーション回路
代表的なFly-Buckアプリケーション回路
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Control Circuit
8.3.2
VCC Regulator
8.3.3
Regulation Comparator
8.3.4
Soft Start
8.3.5
Error Amplifier
8.3.6
On-Time Generator
8.3.7
Current Limit
8.3.8
N-Channel Buck Switch and Driver
8.3.9
Synchronous Rectifier
8.3.10
Enable / Undervoltage Lockout (EN/UVLO)
8.3.11
Thermal Protection
8.4
Device Functional Modes
8.4.1
Forced Pulse Width Modulation (FPWM) Mode
8.4.2
Undervoltage Detector
9
Application and Implementation
9.1
Application Information
9.1.1
Ripple Configuration
9.2
Typical Applications
9.2.1
LM5160 Synchronous Buck (10-V to 60-V Input, 5-V Output, 1.5-A Load)
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Custom Design With WEBENCH® Tools
9.2.1.2.2
Feedback Resistor Divider - RFB1, RFB2
9.2.1.2.3
Switching Frequency - RON
9.2.1.2.4
Inductor - L
9.2.1.2.5
Output Capacitor - COUT
9.2.1.2.6
Series Ripple Resistor - RESR
9.2.1.2.7
VCC and Bootstrap Capacitors - CVCC, CBST
9.2.1.2.8
Input Capacitor - CIN
9.2.1.2.9
Soft-Start Capacitor - CSS
9.2.1.2.10
EN/UVLO Resistors - RUV1, RUV2
9.2.1.3
Application Curves
9.2.2
LM5160 Isolated Fly-Buck (18-V to 32-V Input, 12-V, 4.5-W Isolated Output)
9.2.2.1
LM5160 Fly-Buck Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.2.1
Selection of VOUT1 and Turns Ratio
9.2.2.2.2
Secondary Rectifier Diode
9.2.2.2.3
External Ripple Circuit
9.2.2.2.4
Output Capacitor - COUT2
9.2.2.3
Application Curves
9.2.3
LM5160A Isolated Fly-Buck (18-V to 32-V Input, 12-V, 4.5-W Isolated Output)
9.3
Do's and Don'ts
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
デベロッパー・ネットワークの製品に関する免責事項
12.1.2
開発サポート
12.1.2.1
WEBENCH®ツールによるカスタム設計
12.2
ドキュメントのサポート
12.2.1
関連資料
12.3
関連リンク
12.4
ドキュメントの更新通知を受け取る方法
12.5
コミュニティ・リソース
12.6
商標
12.7
静電気放電に関する注意事項
12.8
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DNT|12
MPDS488B
サーマルパッド・メカニカル・データ
発注情報
jajsgd5e_oa
jajsgd5e_pm
9.2.1.3
Application Curves
Figure 20.
Load Regulation
Figure 22.
EN/UVLO Start-Up at V
IN
= 24 V and I
OUT
= 1 A
Figure 24.
EN/UVLO Start-Up at V
IN
= 24 V and
R
LOAD
= 100 Ω
Figure 26.
Load Transient (300 mA – 1.5 A) at V
IN
= 24 V With Type 3 Ripple Configuration
Figure 21.
Efficiency vs I
OUT
Figure 23.
Prebias Start-Up at V
IN
= 48 V and R
LOAD
= 3 Ω
Figure 25.
Start-Up at V
IN
= 48 V and R
LOAD
= 10 Ω
Figure 27.
Output Short-Circuit at V
IN
= 48 V