JAJSI29A
October 2019 – April 2024
LM5163
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Control Architecture
6.3.2
Internal VCC Regulator and Bootstrap Capacitor
6.3.3
Regulation Comparator
6.3.4
Internal Soft Start
6.3.5
On-Time Generator
6.3.6
Current Limit
6.3.7
N-Channel Buck Switch and Driver
6.3.8
Synchronous Rectifier
6.3.9
Enable/Undervoltage Lockout (EN/UVLO)
6.3.10
Power Good (PGOOD)
6.3.11
Thermal Protection
6.4
Device Functional Modes
6.4.1
Shutdown Mode
6.4.2
Active Mode
6.4.3
Sleep Mode
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Custom Design With WEBENCH® Tools
7.2.2.2
Switching Frequency (RRON)
7.2.2.3
Buck Inductor (LO)
7.2.2.4
Output Capacitor (COUT)
7.2.2.5
Input Capacitor (CIN)
7.2.2.6
Type-3 Ripple Network
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.1.1
Compact PCB Layout for EMI Reduction
7.4.1.2
Feedback Resistors
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
サード・パーティ製品に関する免責事項
8.1.2
Development Support
8.1.2.1
Custom Design With WEBENCH® Tools
8.2
Documentation Support
8.2.1
Related Documentation
8.3
ドキュメントの更新通知を受け取る方法
8.4
サポート・リソース
8.5
Trademarks
8.6
静電気放電に関する注意事項
8.7
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDA|8
MPDS092F
サーマルパッド・メカニカル・データ
DDA|8
PPTD058I
発注情報
jajsi29a_oa
6.2
Functional Block Diagram