7.3.1 Integrated Power MOSFETs

The LM5166 is a step-down buck converter with integrated high-side PMOS buck switch and low-side NMOS synchronous switch. During the high-side MOSFET on-time, the SW voltage V_SW swings up to approximately V_IN, and the inductor current increases with slope (V_IN – V_OUT)/L_F. When the high-side MOSFET is turned off by the control logic, the low-side MOSFET turns on after a fixed dead time. Inductor current flows through the low-side MOSFET with slope –V_OUT/L_F. Duty cycle D is defined as T_ON/T_SW, where T_ON is the high-side MOSFET conduction time and T_SW is the switching period.

7.3.2 Selectable PFM or COT Mode Converter Operation

Depending on how the RT pin is connected, the LM5166 operates in PFM or COT mode. With the RT pin tied to GND, the device operates in PFM mode. An R_RT resistor connected between the RT and GND pins enables COT control and sets the desired switching frequency as defined by Equation 4. Figure 39 and Figure 40 show converter schematics for PFM and COT modes of operation.

Figure 39. PFM Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable Output Voltage With Programmable Soft Start, Current Limit, and UVLO

Figure 40. COT Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable Output Voltage With Programmable Soft Start, Current Limit, and UVLO

7.3.2.1 PFM Mode Operation

In PFM mode, the LM5166 behaves as a hysteretic voltage regulator operating in boundary conduction mode. The output voltage is regulated between upper and lower threshold levels according to the PFM feedback comparator hysteresis of 10 mV. Figure 41 shows the relevant output voltage and inductor current waveforms. The LM5166 provides the required switching pulses to recharge the output capacitor to the upper threshold, followed by a sleep period where most of the internal circuits are disabled. The load current is supported by the output capacitor during this time, and the LM5166 current consumption reduces to 9.7 µA. The sleep period duration depends on load current and output capacitance.

Figure 41. PFM Mode Output Voltage and Inductor Current Representative Waveforms

When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM pulse frequency as

Equation 1.

where

• I_PK(PFM) is one of the programmable levels for peak current limit. See Adjustable Current Limit for more detail.

One of the supported ILIM settings enables a function that modulates the peak current threshold levels during the first three switching cycles of each active period as illustrated in Figure 42. This function improves efficiency under most application conditions at the expense of slightly degraded load transient response.

Figure 42. PFM Mode With Modulated I_LIM, Output Voltage and Inductor Current Representative Waveforms

As expected, the choice of mode and switching frequency represents a compromise between conversion efficiency, quiescent current, and passive component size. Lower switching frequency implies reduced switching losses (including gate charge losses, transition losses, and so forth) and higher overall efficiency. Higher switching frequency, on the other hand, implies smaller LC output filter and hence, a more compact design. Lower inductance also helps transient response and reduces the inductor DCR conduction loss. The ideal switching frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates at lower input quiescent current levels.

7.3.2.2 COT Mode Operation

In COT mode, the LM5166-based converter turns on the high-side MOSFET with constant on-time that adapts to V_IN, as defined by Equation 2, to operate with nearly fixed switching frequency when in continuous conduction mode (CCM). The high-side MOSFET turns on when the feedback voltage (V_FB) falls below the reference voltage. The regulator control loop maintains a constant output voltage by adjusting the PWM off-time as defined with Equation 3. For stable operation, the feedback voltage must decrease monotonically in phase with the inductor current during the off-time as explained in Ripple Generation Methods.

Equation 2.

Equation 3.

Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains high efficiency at light load currents by decreasing the effective switching frequency. The COT-controlled LM5166 waveforms in CCM and DEM are shown in Figure 43.

Figure 43. COT Mode Feedback Voltage and Inductor Current Representative Waveforms

The required on-time adjust resistance for a particular frequency (in CCM) is given in Equation 4 and tabulated in Table 1. The maximum programmable on-time is 15 µs.

Equation 4.

Table 1. On-Time Adjust Resistance (E96 EIA Values) for Various Switching Frequencies and Output Voltages⁽¹⁾

FSW (kHz)	RRT (kΩ)
	VOUT = 1.8 V	VOUT = 3.3 V	VOUT = 5 V	VOUT = 12 V
100	102	187	287	681
200	51.1	95.3	143	340
300	34	63.4	95.3	226
400	25.5	47.5	71.5	169
500	20.5	37.4	57.6	137
600	16.9	31.6	47.5	115

(1) For a more precise adjustment of the switching frequency consider Equation 2 and Equation 3. The LM5166 Quickstart Calculatorl estimates and plots the switching frequency as a function of load current.

7.3.2.2.1 Ripple Generation Methods

In the Constant-On-Time (COT) control scheme, the on-time is terminated by a one-shot, and the off-time is terminated by the feedback voltage (V_FB) falling below the reference voltage (V_FB1). Therefore, for stable operation, the feedback voltage must decrease monotonically in phase with the inductor current during the off-time. Furthermore, this change in feedback voltage (V_FB) during the off-time must be large enough to dominate any noise present at the feedback node.

Table 2. Ripple Generation Methods

TYPE	SCHEMATIC	CALCULATION
Type 1 Lowest Cost		Equation 5. Equation 6.
Type 2 Reduced Ripple		Equation 7. Equation 8. Equation 9.
Type 3(1) Lowest Ripple		Equation 10. Equation 11. Equation 12.

(1) Lin, Min and others, "Frequency Domain Analysis of Fixed On-Time With Bottom Detection Control for Buck Converter," IEEE IECON 2010, pp. 481–485.

Table 2 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1 ripple generation method uses a single resistor, designated R_ESR, in series with the output capacitor. The generated voltage ripple has two components:

• Capacitive ripple caused by the inductor ripple current charging and discharging the output capacitor.
• Resistive ripple caused by the inductor ripple current flowing in the output capacitor ESR and series resistance R_ESR.

The capacitive ripple component is out of phase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the off-time. The resistive ripple component is in phase with the inductor current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output (V_OUT) for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off-time. Equation 5 and Equation 6 define the value of the R_ESR resistor that ensures the required amplitude and phase of the ripple at the feedback node.

Type-2 ripple generation method uses a C_FF capacitor in addition to the R_ESR resistor. As the output voltage ripple is directly AC-coupled by C_FF to the feedback node, the R_ESR value and ultimately the output voltage ripple are reduced by a factor of V_OUT / V_FB1.

Type-3 ripple generation method uses an RC network consisting of R_A and C_A, and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is then AC-coupled into the feedback node (FB) with capacitor C_B. Because this circuit does not use the output voltage ripple, it is suited for applications where low output voltage ripple is critical. Application note AN-1481 Controlling Output Ripple & Achieving ESR Independence in Constant On-Time Regulator Designs provides additional details on this topic.

7.3.2.2.2 COT Mode Light-Load Operation

Diode emulation mode (DEM) operation occurs when the low-side MOSFET switches off as the inductor valley current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current reduces switching loss, and preventing negative current conduction reduces conduction loss. In DEM, the duration that both high-side and low-side MOSFETs remain off progressively increases as load current decreases.

7.3.3 Low Dropout Operation and 100% Duty Cycle Mode

Using R_DSON1 and R_DSON2 for the high-side and low-side MOSFET on-state resistances, respectively, and R_DCR for the inductor DC resistance, the duty cycle in COT (CCM) or PFM mode is given by Equation 13.

Equation 13.

The LM5166 provides a low input voltage to output voltage dropout by engaging the high-side MOSFET at 100% duty cycle. In COT operation, the extended on-time mode seamlessly increases the duty cycle during low dropout conditions or load-step transients. The buck switch on-time extends based on the requirement that the FB voltage exceeds the internal 4-mV FB comparator hysteresis during any COT mode on-time. The on-time (and duty cycle) are extended as needed at low input voltage conditions until the FB voltage reaches the upper threshold. 100% duty cycle operation is eventually reached as the input voltage decreases to a level near the output voltage setpoint. Very low dropout voltages can be achieved with 100% duty cycle and a low DCR inductor.

Note that PFM mode operation provides a natural transition to 100% duty cycle if needed during low input voltage conditions. If the input-to-output voltage difference is very low, the inductor current increases to a level determined by the load and may not reach the peak current threshold required to turn off the buck switch.

Use Equation 14 to calculate the minimum input voltage to maintain output regulation at 100% duty cycle.

Equation 14.

7.3.4 Adjustable Output Voltage (FB)

Three voltage feedback settings are available. The fixed 3.3-V and 5-V versions include internal feedback resistors that sense the output directly through the VOUT pin, and the adjustable voltage option senses the output through an external resistor divider connected from the output to the FB pin.

The LM5166 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage (V_FB1). A resistor divider programs the ratio from output voltage V_OUT to FB. For a target V_OUT setpoint, calculate R_FB2 based on the selected R_FB1 by Equation 15.

Equation 15.

R_FB1 in the range of 100 kΩ to 1 MΩ is recommended for most applications. A larger R_FB1 consumes less DC current, which is necessary if light-load efficiency is critical. However, R_FB1 larger than 1 MΩ is not recommended as the feedback path becomes more susceptible to noise. Larger feedback resistances generally require more careful feedback path PCB layout. It is important to route the feedback trace away from the noisy area of the PCB. For more PCB layout recommendations, see Layout.

7.3.5 Adjustable Current Limit

The LM5166 protects the system from overload conditions using cycle-by-cycle current limiting of the peak inductor current. The current sensed in the high-side MOSFET is compared to the current limit threshold set by the ILIM pin (see Table 3). Current is sensed after a 120-ns leading-edge blanking time following the high-side MOSFET turnon. The propagation delay of the current limit comparator is 80 ns, typical.

Note that in PFM mode, the inductor current ramps from zero to the chosen peak threshold every switching cycle. Consequently, the maximum output current is equal to half the peak inductor current. The output current capability in COT mode is higher and equal to the peak current threshold minus one-half the inductor ripple current. The ripple current is determined by the input and output voltages and the chosen inductance and switching frequency.

7.3.6 Precision Enable (EN) and Hysteresis (HYS)

The precision EN input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed independently through the HYS pin for application specific power-up and power-down requirements. EN connects to the input of a comparator with 76-mV hysteresis. The reference input of the comparator is connected to a 1.22-V bandgap reference. An external logic signal can be used to drive EN input to toggle the output on and off for system sequencing or protection. The simplest way to enable operation is to connect EN directly to VIN. This allows self-start-up of the LM5166 when V_IN is within its valid operating range.

Figure 44. Input Voltage UVLO Using EN and HYS

However, many applications benefit from using a resistor divider R_UV1 and R_UV2 as shown in Figure 44 to establish a precision UVLO level. Adding R_HYS and the connection to the HYS pin increases the voltage hysteresis as needed.

The input UVLO voltages are calculated using Equation 16 and Equation 17.

Equation 16.

Equation 17.

The LM5166 enters a low I_Q shutdown mode when EN is pulled below an NPN transistor base-emitter voltage drop (approximately 0.6 V at room temperature). If EN is below this hard shutdown threshold, the internal LDO regulator powers off and the internal bias supply rail collapses, turning off the bias currents of the LM5166.

7.3.7 Power Good (PGOOD)

The LM5166 has a built-in PGOOD flag to indicate whether the output voltage is within a regulation window. The PGOOD signal can be used for start-up sequencing of downstream converters, as shown in Figure 45, or fault protection. PGOOD is an open-drain output that requires a pullup resistor to a DC supply (12 V maximum). Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the PGOOD pin voltage from a higher pullup rail.

Figure 45. Master-Slave Sequencing Implementation Using PGOOD and EN

When the FB voltage exceeds 94% of the internal reference V_FB1, the PGOOD switch turns off and PGOOD will be pulled high. If the FB voltage falls below 87% of V_FB1, the PGOOD switch turns on, and PGOOD pulls low to indicate power bad. The rising edge of PGOOD has a built-in noise filter delay of 5 µs.

7.3.8 Configurable Soft Start (SS)

The LM5166 has a flexible and easy-to-use start-up control through the SS pin. A soft-start feature prevents inrush current impacting the LM5166 and its supply when power is first applied. Soft start is achieved by slowly ramping up the target regulation voltage when the device is enabled or powered up. Selectable and adjustable soft-start timing options include minimum delay (no soft-start), 900-µs internally fixed soft-start, and an externally-adjustable soft start.

The simplest way to use the LM5166 is to leave the SS pin open circuit for a 900-µs soft-start time. The LM5166 will employ the internal soft-start control ramp and start-up to the regulated output voltage. In applications with a large amount of output capacitors, higher V_OUT, or other special requirements, extend the soft-start time by connecting an external capacitor C_SS from SS to GND. Longer soft-start time further reduces the supply current needed to charge the output capacitors. An internal current source (I_SS = 10 µA) charges C_SS and generates a ramp to control the ramp rate of the output voltage. For a desired soft-start time t_SS, the C_SS capacitance is:

Equation 18.

C_SS is discharged by an internal 80-Ω FET when V_OUT is shutdown by EN, UVLO, or thermal shutdown.

It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit of the LM5166, and the LM5166 operates in current limit during start-up to rapidly charge the output capacitance.

Diode emulation mode (DEM) of the LM5166 prevents negative inductor current enabling monotonic start-up under prebiased output conditions. With a prebiased output voltage, the LM5166 waits until the soft-start ramp allows regulation above the prebiased voltage and then follows the soft-start ramp to the regulation setpoint as shown in Figure 46 and Figure 47.

Time Scale: 2 ms/Div CH1: VEN, 1 V/Div

CH2: VOUT, 1 V/Div CH4: IOUT, 200 mA/Div

Figure 46. ENABLE On and Off; V_OUT Prebiased to 1.8 V
Figure 52 Circuit, V_IN = 24 V, No Load

Time Scale: 2 ms/Div CH1: VEN, 5 V/Div

CH2: VOUT, 1 V/Div CH4: IOUT, 200 mA/Div

Figure 47. ENABLE On and Off; V_OUT Prebiased to 1.8 V
Figure 52 Circuit, V_IN = 24 V, 500 mA Load

7.3.9 Short-Circuit Operation

The LM5166 features a clamping circuit that clamps the SS voltage about 175 mV above the FB voltage (see Figure 48 and Figure 49). The circuit is enabled in COT mode and only works when an external soft-start capacitor is connected.

Figure 48. Soft-Start (SS) Voltage vs Feedback (FB) Voltage

Figure 49. Soft-Start to Feedback Clamp Offset vs Temperature

In case of an overload event such as an output short circuit, the clamping circuit discharges the soft-start capacitor. When the short is removed, the FB voltage quickly rises until it reaches the level of the SS pin. Then, the recovery continues under the soft-start capacitor control. Figure 50 and Figure 51 show short-circuit entry and recovery waveforms.

Time Scale: 1 ms/Div

CH2: VOUT, 2 V/Div CH4: IL, 200 mA/Div

Figure 50. Short-Circuit Entry
(Figure 52 Circuit)

Time Scale: 1 ms/Div

CH2: VOUT, 2 V/Div CH4: IL, 200 mA/Div

Figure 51. Short-Circuit Recovery
(Figure 52 Circuit)

7.3.10 Thermal Shutdown

Thermal shutdown is a built-in self protection to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C typically to prevent further power dissipation and temperature rise. Junction temperature decreases during thermal shutdown, and the LM5166 restarts when the junction temperature falls to 160°C.

7.4.1 Shutdown Mode

The EN pin provides ON / OFF control for the LM5166. When V_EN is below 0.3 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 4 µA (typical) at V_IN = 12 V. The LM5166 also includes undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below the UV threshold level, the switching regulator remains off.

7.4.2 Standby Mode

The internal bias LDO has a lower enable threshold than the switching regulator. When V_EN is above 0.6 V and below the precision enable threshold (1.22 V typically), the internal LDO is on and regulating. The precision enable circuitry is turned on if the LDO output is above the bias rail UV threshold. The switching action and output voltage regulation are disabled in the standby mode.

7.4.3 Active Mode – COT

The LM5166 is in active mode when V_EN is above the precision enable threshold and the internal bias rail is above its UV threshold level. In COT active mode, the LM5166 operates in one of three modes depending on the load current:

1. CCM with fixed switching frequency when the load current is more than half of the peak-to-peak inductor current ripple;
2. Pulse skipping and diode emulation mode when load current is less than half of the peak-to-peak inductor current ripple of CCM operation;
3. Extended on-time mode when V_IN is nearly equal to V_OUT (dropout) and during load step transients.

7.4.4 Sleep Mode – COT

The LM5166 is in COT sleep mode when V_EN and V_IN are above their relevant threshold levels, FB has exceeded its upper hysteresis level, and the output capacitor is sourcing the load current. In COT sleep mode, the LM5166 operates with very low quiescent current (9.7 µA typical). There is a 2-µs wake-up delay from sleep to active modes.

7.4.5 Active Mode – PFM

The LM5166 is in PFM active mode when V_EN and V_IN are above their relevant thresholds, FB has fallen below the lower hysteresis level, and boundary conduction mode switching is recharging the output capacitor to the upper hysteresis level.

7.4.6 Sleep Mode – PFM

The LM5166 is in PFM sleep mode when V_EN and V_IN are above their relevant threshold levels, FB has exceeded the upper hysteresis level, and the output capacitor is sourcing the load current. In PFM sleep mode, the LM5166 operates with very low quiescent current (9.7 µA typical). There is a 2-µs wake-up delay from sleep to active modes.