The I ² C bus is a communications link between a Controller and a series of Peripheral devices. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the Controller in all cases where the serial data line is bi-directional for data communication between the Controller and the Peripheral terminals. Each device has an open-drain output to transmit data on the serial data line (SDA). An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. The device hosts a Peripheral I ² C interface that supports standard-mode, fast-mode and fast-mode plus operation with data rates up to 100kbit/s, 400 kbit/s and 1000 kbit/s respectively and auto-increment addressing compatible to I ² C standard 3.0. Data transmission is initiated with a start bit from the controller as shown in the figure below. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device receives serial data on the SDA input and check for valid address and control information. If the peripheral address bits are set for the device, then the device issues an acknowledge pulse and prepares to receive the register address and data. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I ² C interfaces auto-sequence through register addresses, so that multiple data words can be sent for a given I ² C transmission.