The device features an internal phase looked loop (PLL), which is designed to transition the switching frequency seamlessly between the frequency set by the RT pin and the external frequency synchronization signal. If no external frequency is provided, the RT pin sets the center frequency of the PLL. The external synchronization signal can change the switching frequency ±50%. To ensure low quiescence current, the input buffer of the SYNC pin is disabled if no valid sync frequency, that is a frequency signal outside the recommended synchronization range is applied.

If a valid synchronization frequency is applied, the device does not enter uSleep during the PSM pause. The internal PLL is kept active to quickly re-syncs to the external synchronization signal in case of a increased load e.g. due to a load step on the output. This behavior improves the transient responds but causes higher quiescent currents for light load operation because the uSleep is disabled if a synchronization signal is provide to the SYNC pin.

The synchronization timings are given in Figure 8-13.

Figure 8-12 Main Oscillator Functional Block Diagram

Figure 8-13 Timing Diagram SYNC Function

The sync pin has a dual function to configure the current limit direction during the initialization phase. If pulled low during this time the negative current limit is selected. Otherwise the positive current limit is selected.