JAJSRI9B October   2023  – June 2024 LM51772

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck-Boost Control Scheme
        1. 7.3.1.1 Buck Mode
        2. 7.3.1.2 Boost Mode
        3. 7.3.1.3 Buck-Boost Mode
      2. 7.3.2  Power Save Mode
      3. 7.3.3  Programmable Conduction Mode PCM
      4. 7.3.4  Reference System
        1. 7.3.4.1 VIO LDO and nRST-PIN
      5. 7.3.5  Supply Voltage Selection – VSMART Switch and Selection Logic
      6. 7.3.6  Enable and Undervoltage Lockout
        1. 7.3.6.1 UVLO
        2. 7.3.6.2 VDET Comparator
      7. 7.3.7  Internal VCC Regulators
        1. 7.3.7.1 VCC1 Regulator
        2. 7.3.7.2 VCC2 Regulator
      8. 7.3.8  Error Amplifier and Control
        1. 7.3.8.1 Output Voltage Regulation
        2. 7.3.8.2 Output Voltage Feedback
        3. 7.3.8.3 Voltage Regulation Loop
        4. 7.3.8.4 Dynamic Voltage Scaling
      9. 7.3.9  Output Voltage Discharge
      10. 7.3.10 Peak Current Sensor
      11. 7.3.11 Short Circuit - Hiccup Protection
      12. 7.3.12 Current Monitor/Limiter
        1. 7.3.12.1 Overview
        2. 7.3.12.2 Output Current Limitation
        3. 7.3.12.3 Output Current Monitor
      13. 7.3.13 Oscillator Frequency Selection
      14. 7.3.14 Frequency Synchronization
      15. 7.3.15 Output Voltage Tracking
        1. 7.3.15.1 Analog Voltage Tracking
        2. 7.3.15.2 Digital Voltage Tracking
      16. 7.3.16 Slope Compensation
      17. 7.3.17 Configurable Soft Start
      18. 7.3.18 Drive Pin
      19. 7.3.19 Dual Random Spread Spectrum – DRSS
      20. 7.3.20 Gate Driver
      21. 7.3.21 Cable Drop Compensation (CDC)
      22. 7.3.22 CFG-pin and R2D Interface
      23. 7.3.23 Advanced Monitoring Features
        1. 7.3.23.1  Overview
        2. 7.3.23.2  BUSY
        3. 7.3.23.3  OFF
        4. 7.3.23.4  VOUT
        5. 7.3.23.5  IOUT
        6. 7.3.23.6  INPUT
        7. 7.3.23.7  TEMPERATURE
        8. 7.3.23.8  CML
        9. 7.3.23.9  OTHER
        10. 7.3.23.10 ILIM_OP
        11. 7.3.23.11 nFLT/nINT Pin Output
        12. 7.3.23.12 Status Byte
      24. 7.3.24 Protection Features
        1. 7.3.24.1  Thermal Shutdown (TSD)
        2. 7.3.24.2  Over Current Protection
        3. 7.3.24.3  Output Over Voltage Protection 1 (OVP1)
        4. 7.3.24.4  Output Over Voltage Protection 2 (OVP2)
        5. 7.3.24.5  Input Voltage Protection (IVP)
        6. 7.3.24.6  Input Voltage Regulation (IVR)
        7. 7.3.24.7  Power Good
        8. 7.3.24.8  Boot-Strap Under Voltage Protection
        9. 7.3.24.9  Boot-strap Over Voltage Clamp
        10. 7.3.24.10 CRC - CHECK
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overview
      2. 7.4.2 Logic State Description
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. 8 LM51772 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Slope Compensation
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Loop Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate Driver Layout
        3. 9.4.1.3 Controller Layout
      2. 9.4.2 Layout Example
    5. 9.5 USB-PD Source with Power Path
    6. 9.6 Parallel (Multiphase) Operation
    7. 9.7 Constant Current LED Driver
    8. 9.8 Wireless Charging Supply
    9. 9.9 Bi-Directional Power Backup
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions


LM51772 RHA Package 40-Pin QFN Top View

Figure 4-1 RHA Package 40-Pin QFN Top View
Table 4-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
VCC1 1 O Auxiliary 5V regulator output. Place a capacitor close to the pin for good decoupling. If the output is disabled by the logic it can be tied to GND with a resistor or pulled to VCC2. Do not leave the pin floating.
SS/ATRK 2 I/O Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.

Analog output voltage tracking pin. The VOUT regulation target can be programmed by connecting the pin to variable voltage reference (for example, through a digital to analog converter). The internal circuit selects the lowest voltage between the pin voltage and the internal voltage reference.
SYNC 3 I Synchronization clock input/output. The internal oscillator can be synchronized to an external clock during operation. Do not leave this pin floating. If this function is not used, connect the pin to VCC2 or GND.

The SYNC pin can be configured as clock synchronization output signal. The clock phase can be selected to 0° and 180° to directly operate two devices in a parallel (dual phase) operation.
DTRK 4 I Digital PWM input pin for the dynamic output voltage tracking. Do not leave this pin floating. If this function is not used, connect the pin to VCC or GND.
SDA/CFG3 5 I/O I2C interface serial data line. Connect an external a pull-up resistor

If I2C is disabled, this pin is a further configuration pin. Connect a resistor between the CFG3-pin and AGND to select the device operation according Section 7.3.22
SCL/CFG4 6 I I2C interface serial clock line. Connect an external a pull-up resistor

If I2C is disabled, this pin is a further configuration pin. Connect a resistor between the CFG4-pin and AGND to select the device operation according Section 7.3.22
MODE 7 I Digital input to select device operation mode. If the pin is pulled low, power save mode (PSM) is enabled. If the pin is pulled high, the forced PWM or CCM operation is enabled. The configuration can be changed dynamically during operation. Do not leave this pin floating.
CFG2 8 I/O Device configuration pin. Connect a resistor between the CFG2 pin and GND to select the device operation according the Section 7.3.22
ADDR/SLOPE(CFG1) 9 I

Slope Compensation and Address selection. This pin also disables the I2C interface to use the SCL, SCA as additional slope configuration pins.

Connect a resistor between the CFG1 pin and AGND to select the device operation according Section 7.3.22
CDC 10 Cable drop compensation or current monitor output pin. Connect a resistor between the CDC pin and AGND to select the gain for the cable drop compensation.

Per default this pin provides a current monitoring signal of the sensed voltage between the ISNSP and ISNSN pins

In case the current monitor is disabled connect CDC to ground
nFLT/nINT 11 O Open-drain output pin for fault indication or power good. This pin can be configured as interrupt pin. In case of a STATUS register change the pin toggles low for 256μs.
RT 12 I/O Switching frequency programming pin. An external resistor is connected to the RT pin and AGND to set the switching frequency
COMP 13 O Output of the error amplifier. An external RC network needs to be connected between COMP and AGND to stabilize/compensate the regulator voltage loop.
FB/SEL_intFB 14 I Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin. Connect the FB pin to VCC2 to operate at a fixed output voltage default setting of the device.

To select the internal feedback connect the pin to VCC2 before the device start-up
VIN-FB 15

VIN sense pin. Connect to a VIN divider with the same gain as the VOUT divider for using PCM with external divider.

If the internal Vout divider or if PCM is not used, connect to AGND. Do not leave floating.
ILIMCOMP/ISET 16 Compensation pin for average current limit loop. Connect an capacitor or a type 2 R-C network if the current limit is set by the internal DAC.

If the internal DAC is disabled the pin sets the current limit threshold for the average current limit. Connect a resistor to AGND. A parallel filter of capacitor is recommended depending on the application requirements

Connect a resistor to AGND if the current limit is set by ISET.

Connect the ISET pin to VCC2 to disable the block and reduce the quiescent current

AGND 17 G Analog Ground
VOUT 18 I Output voltage sense input. Connect to the power stage output rail.
ISNSN 19 I Negative sense input of the output or input average current sense amplifier. An optional current sense resistor connected between ISNSN and ISNSP can be located either on the input side or on the output side of the power stage.

In case the optional current sensor is disabled connect ISNSN and ISNSP together to AGND

ISNSP 20 I Positive sense input of the output or input current sense amplifier. An optional current sense resistor connected between ISNSN and ISNSP can be placed either on the input side or on the output side of the power stage.

In case the optional current sensor is disabled connect ISNSP to ground
CSB 21 I Inductor peak current sense negative input. Connect CSB to the negative side of the external current sense resistor using a Kelvin connection.
CSA 22 I Inductor peak current sense positive input. Connect CSA to the positive side of the external current sense resistor using a Kelvin connection.
SW1 23 P Inductor switch node for the buck half-bridge
HO1 24 O High-side gate driver output for the buck half-bridge
HB1 25 P Bootstrap supply pin for buck half-bridge. An external capacitor is required between the HB1 pin and the SW1 pin, to provide bias to the high-side MOSFET gate driver.

Place the external capacitor close to the pin without any resistance between the pin and capacitor for good decoupling
NC 26 O Not Connected
LO1 27 O Low-side gate driver output for the buck half-bridge
PGND 28 G Power Ground
VCC2 29 O Internal linear bias regulator output. Connect a ceramic decoupling capacitor from VCC to PGND. This rail supplies the internal logic and the gate driver.

Place the external capacitor close to the pin without any resistance between the pin and capacitor for good decoupling.
LO2 30 O Low-side gate driver output for the boost half-bridge
HB2 31 P Bootstrap supply pin for boost half-bridge. An external capacitor is required between the HB2 pin and the SW2 pin, to provide bias to the high-side MOSFET gate driver

Place the external capacitor close to the pin without any resistance between the pin and capacitor for good decoupling
HO2 32 O High-side gate driver output for the boost half-bridge
SW2 33 P Inductor switch node for the buck half-bridge
NC 34 O Not Connected
DRV1 35 External FET drive pin. This pin features a high-voltage push pull stage, a open drain output or a charge pump driver stage according to the selected configuration.

In case the optional DRV pin is not used you can leave DRV open.
VIN 36 I The input supply and sense input of the device. Connect VIN to the supply voltage of the power stage.
EN/UVLO 37 I Enable pin. Digital input pin to enable the converter switching.

The input features a precise analog comparator and a hysteresis to monitor the input voltage. Connect a resistor divider from the input voltage to maintain the under voltage lookout(UVLO) feature.
nRST 38 I Digital input pin to enable the device internal logic, interface operation and the VCC1 regulator if selected.
NC 39 O Not Connected
BIAS 40 Optional input to the VCC2 bias regulator. Powering VCC2 from an external supply instead of VIN can reduce power loss at high VIN.
GND PAD G Thermal pad
  1. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.