JAJSRI9B
October 2023 – June 2024
LM51772
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Handling Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Buck-Boost Control Scheme
7.3.1.1
Buck Mode
7.3.1.2
Boost Mode
7.3.1.3
Buck-Boost Mode
7.3.2
Power Save Mode
7.3.3
Programmable Conduction Mode PCM
7.3.4
Reference System
7.3.4.1
VIO LDO and nRST-PIN
7.3.5
Supply Voltage Selection – VSMART Switch and Selection Logic
7.3.6
Enable and Undervoltage Lockout
7.3.6.1
UVLO
7.3.6.2
VDET Comparator
7.3.7
Internal VCC Regulators
7.3.7.1
VCC1 Regulator
7.3.7.2
VCC2 Regulator
7.3.8
Error Amplifier and Control
7.3.8.1
Output Voltage Regulation
7.3.8.2
Output Voltage Feedback
7.3.8.3
Voltage Regulation Loop
7.3.8.4
Dynamic Voltage Scaling
7.3.9
Output Voltage Discharge
7.3.10
Peak Current Sensor
7.3.11
Short Circuit - Hiccup Protection
7.3.12
Current Monitor/Limiter
7.3.12.1
Overview
7.3.12.2
Output Current Limitation
7.3.12.3
Output Current Monitor
7.3.13
Oscillator Frequency Selection
7.3.14
Frequency Synchronization
7.3.15
Output Voltage Tracking
7.3.15.1
Analog Voltage Tracking
7.3.15.2
Digital Voltage Tracking
7.3.16
Slope Compensation
7.3.17
Configurable Soft Start
7.3.18
Drive Pin
7.3.19
Dual Random Spread Spectrum – DRSS
7.3.20
Gate Driver
7.3.21
Cable Drop Compensation (CDC)
7.3.22
CFG-pin and R2D Interface
7.3.23
Advanced Monitoring Features
7.3.23.1
Overview
7.3.23.2
BUSY
7.3.23.3
OFF
7.3.23.4
VOUT
7.3.23.5
IOUT
7.3.23.6
INPUT
7.3.23.7
TEMPERATURE
7.3.23.8
CML
7.3.23.9
OTHER
7.3.23.10
ILIM_OP
7.3.23.11
nFLT/nINT Pin Output
7.3.23.12
Status Byte
7.3.24
Protection Features
7.3.24.1
Thermal Shutdown (TSD)
7.3.24.2
Over Current Protection
7.3.24.3
Output Over Voltage Protection 1 (OVP1)
7.3.24.4
Output Over Voltage Protection 2 (OVP2)
7.3.24.5
Input Voltage Protection (IVP)
7.3.24.6
Input Voltage Regulation (IVR)
7.3.24.7
Power Good
7.3.24.8
Boot-Strap Under Voltage Protection
7.3.24.9
Boot-strap Over Voltage Clamp
7.3.24.10
CRC - CHECK
7.4
Device Functional Modes
7.4.1
Overview
7.4.2
Logic State Description
7.5
Programming
7.5.1
I2C Bus Operation
7.5.2
Clock Stretching
7.5.3
Data Transfer Formats
7.5.4
Single READ from a Defined Register Address
7.5.5
Sequential READ Starting from a Defined Register Address
7.5.6
Single WRITE to a Defined Register Address
7.5.7
Sequential WRITE Starting at a Defined Register Address
8
LM51772 Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Custom Design with WEBENCH Tools
9.2.2.2
Frequency
9.2.2.3
Feedback Divider
9.2.2.4
Inductor and Current Sense Resistor Selection
9.2.2.5
Output Capacitor
9.2.2.6
Input Capacitor
9.2.2.7
Slope Compensation
9.2.2.8
UVLO Divider
9.2.2.9
Soft-Start Capacitor
9.2.2.10
MOSFETs QH1 and QL1
9.2.2.11
MOSFETs QH2 and QL2
9.2.2.12
Loop Compensation
9.2.2.13
External Component Selection
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Power Stage Layout
9.4.1.2
Gate Driver Layout
9.4.1.3
Controller Layout
9.4.2
Layout Example
9.5
USB-PD Source with Power Path
9.6
Parallel (Multiphase) Operation
9.7
Constant Current LED Driver
9.8
Wireless Charging Supply
9.9
Bi-Directional Power Backup
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHA|40
MPQF135D
サーマルパッド・メカニカル・データ
RHA|40
QFND660
発注情報
jajsri9b_oa
5
Specifications