SNAS548D February   2000  – January 2015 LM555

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Direct Replacement for SE555/NE555
      2. 7.3.2 Timing From Microseconds Through Hours
      3. 7.3.3 Operates in Both Astable and Monostable Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Monostable Operation
      2. 7.4.2 Astable Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Frequency Divider
        2. 8.2.2.2 Additional Information
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Direct Replacement for SE555/NE555
  • Timing from Microseconds through Hours
  • Operates in Both Astable and Monostable Modes
  • Adjustable Duty Cycle
  • Output Can Source or Sink 200 mA
  • Output and Supply TTL Compatible
  • Temperature Stability Better than 0.005% per °C
  • Normally On and Normally Off Output
  • Available in 8-pin VSSOP Package

2 Applications

  • Precision Timing
  • Pulse Generation
  • Sequential Timing
  • Time Delay Generation
  • Pulse Width Modulation
  • Pulse Position Modulation
  • Linear Ramp Generator

3 Description

The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200 mA or drive TTL circuits.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM555 SOIC (8) 4.90 mm × 3.91 mm
PDIP (8) 9.81 mm × 6.35 mm
VSSOP (8) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Schematic Diagram

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