JAJSKY7A February   2020  – November 2021 LM61480 , LM61495 , LM62460

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Voltage Selection
      2. 8.3.2  Enable EN Pin and Use as VIN UVLO
      3. 8.3.3  SYNC/MODE Uses for Synchronization
      4. 8.3.4  Clock Locking
      5. 8.3.5  Adjustable Switching Frequency
      6. 8.3.6  RESET Output Operation
      7. 8.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 8.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 8.3.9  Adjustable SW Node Slew Rate
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Hiccup
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 Peak Current Mode Operation
        2. 8.4.3.2 Auto Mode Operation
          1. 8.4.3.2.1 Diode Emulation
        3. 8.4.3.3 FPWM Mode Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
        6. 8.4.3.6 Recovery from Dropout
        7. 8.4.3.7 Other Fault Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  CFF and RFF Selection
        10. 9.2.2.10 RSPSP Selection
        11. 9.2.2.11 RT Selection
        12. 9.2.2.12 RMODE Selection
        13. 9.2.2.13 External UVLO
        14. 9.2.2.14 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.6 RESET Output Operation

While the RESET function of the LM6x4xx resembles a standard power-good function, the functionality is designed to replace a discrete reset IC, reducing BOM cost. There are three major differences between the reset function and the normal power-good function seen in most regulators:

  • A delay has been added for release of reset. See Table 8-1.
  • RESET output signals a fault (pulls its output to ground) while the part is disabled.
  • RESET continues to operate with input voltage as low as 1.2 V. Below this input voltage, RESET output can be high impedance.
GUID-BB901BA3-5E8F-4621-ADCB-73417A5B9523-low.gifFigure 8-7 RESET Static Voltage Thresholds
GUID-046CCB47-5269-4A19-868F-96F66F37A16B-low.gifFigure 8-8 RESET Timing Diagram (Excludes OV Events)
Table 8-1 Conditions that Cause RESET to Signal a Fault (Pull Low)
FAULT CONDITION INITIATEDFAULT CONDITION ENDS (AFTER WHICH tRESET_ACT MUST PASS BEFORE RESET OUTPUT IS RELEASED)
FB below VRESET_UV for longer than tRESET_FILTERFB above VRESET_UV + VRESET_HYST for longer than tRESET_FILTER
FB above VRESET_OV for longer than tRESET_FILTERFB below VRESET_OV - VRESET_HYST for longer than tRESET_FILTER
Junction temperature exceeds TSD_RJunction temperature falls below TSD_F(1)
EN lowtEN passes after EN becomes high(1)
VIN falls low enough so that VCC falls below VCC_UVLO - VCC_UVLO_HYST. This value is called VIN_OPERATE.Voltage on VIN is high enough so that VCC pin exceed VCC_UVLO(1)
(1) As an additional operational check, RESET remains low during soft start. It is defined as until the lesser of either full output voltage reached or tSS2 has passed since initiation. This is true even if all other conditions in this table are met and tRESET_ACT has passed. Lockout during soft start does not require tRESET_ACT to pass before RESET is released.

The threshold voltage for the RESET function is specified to take advantage of the availability of the LM6x4xx internal feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected output voltage to be specified at the same time as 96% of actual operating point. The net result is a more accurate reset function while expanding the system allowance for transient response. See the output voltage error stack-up comparison in Figure 8-9.

In addition to signaling a fault upon overvoltage detection (FB above VRESET_OV), the switch node is shut down and a small, approximately 1-mA pulldown is applied to the SW node.

GUID-43E6F26F-CD93-4466-AE5E-762A835F20CB-low.gifFigure 8-9 Reset Threshold Voltage Stack-up