JAJSKY7A February   2020  – November 2021 LM61480 , LM61495 , LM62460

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Voltage Selection
      2. 8.3.2  Enable EN Pin and Use as VIN UVLO
      3. 8.3.3  SYNC/MODE Uses for Synchronization
      4. 8.3.4  Clock Locking
      5. 8.3.5  Adjustable Switching Frequency
      6. 8.3.6  RESET Output Operation
      7. 8.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 8.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 8.3.9  Adjustable SW Node Slew Rate
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Hiccup
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 Peak Current Mode Operation
        2. 8.4.3.2 Auto Mode Operation
          1. 8.4.3.2.1 Diode Emulation
        3. 8.4.3.3 FPWM Mode Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
        6. 8.4.3.6 Recovery from Dropout
        7. 8.4.3.7 Other Fault Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  CFF and RFF Selection
        10. 9.2.2.10 RSPSP Selection
        11. 9.2.2.11 RT Selection
        12. 9.2.2.12 RMODE Selection
        13. 9.2.2.13 External UVLO
        14. 9.2.2.14 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-C96249BE-2F32-4AF0-BA13-B21E78FE1773-low.gif Figure 6-1 16-Pin VQFNRPH Package(Top View)
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
PGND2 1 G Power ground to internal low-side MOSFET. Connect to system ground. Low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
VIN2 2 P Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. Provide a low-impedance connection to VIN1.
RBOOT 3 P Connect to CBOOT through a resistor. A resistance, typically between 0 Ω and 100 Ω, is used to adjust the slew rate of the SW node rise time. See Figure 8-10.
CBOOT 4 P High-side driver upper supply rail. Connect a 100-nF capacitor between the SW pin and CBOOT. An internal diode charges the capacitor while SW node is low.
BIAS 5 P Input to internal voltage regulator. Connect the pin to an output voltage point or an external bias supply from 3.3 V to 12 V. Connect an optional high-quality 0.1-µF capacitor from this pin to GND for the best performance. If output voltage is above 12 V and no external supply is used, tie the pin to ground.
VCC 6 O Internal regulator output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Connect a high-quality 1-µF capacitor from this pin to AGND.
FB 7 I Feedback input to regulator. Connect this pin to an output voltage sense point for fixed output versions (for example, 3.3 V and 5 V). Connect this pin to a feedback divider tap point for adjustable output options. Do not float or ground.
AGND 8 G Analog ground for regulator and system. All electrical parameters are measured with respect to this pin. Connect this pin to PGND1 and PGND2 on PCB.
RT 9 I/O Connect this pin to ground through a resistor with a value between 6.8 kΩ and 80 kΩ to set the switching frequency between 200 kHz and 2200 kHz. Connect to VCC for 400 kHz. Connect to GND for 2.2 MHz. Do not float.
RESET 10 O Open-drain RESET output. Connect to a suitable voltage supply through a current limiting resistor. High = power OK, low = fault. RESET goes low when EN = low.
SPSP 11 I Connect to VCC or through a resistor to ground to enable spread spectrum. Connect to GND to disable spread spectrum. If using spread spectrum, a VCC connection turns off the spread spectrum tone correction while a resistor to ground adjusts the tone correction to lower the output voltage ripple. Do not float this pin. See Section 8.3.10.
SYNC/MODE 12 I This pin controls the mode of operation of the LM6x4xx. Modes include Auto mode (automatic PFM/PWM operation), forced pulse width modulation (FPWM), and synchronized to an external clock. The clock triggers on the rising edge of an applied external clock. Pull low to enable PFM operation, pull high to enable FPWM, or connect to a clock to synchronize to an external frequency in FPWM mode. Do not float this pin.
When synchronized to an external clock, use the RT pin to set the internal frequency close to the synchronized frequency to avoid disturbances if the external clock is turned on and off.
EN 13 I Precision enable input to regulator. High = on, low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. Do not float. See Section 8.3.2.
VIN1 14 P Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. Low-impedance connection must be provided to VIN2.
PGND1 15 G Power ground to internal low-side MOSFET. Connect to system ground. Low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
SW 16 P Switch node of the regulator. Connect to the output inductor.