JAJSJO6C December   2021  – August 2024 LM63440-Q1 , LM63460-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 5.1 Wettable Flanks
    2. 5.2 Pinout Design for Clearance and FMEA
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Systems Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Output Voltage Setpoint (FB)
      3. 7.3.3  Precision Enable and Input Voltage UVLO (EN/SYNC)
      4. 7.3.4  Frequency Synchronization (EN/SYNC)
      5. 7.3.5  Clock Locking
      6. 7.3.6  Adjustable Switching Frequency (RT)
      7. 7.3.7  Power-Good Monitor (PGOOD)
      8. 7.3.8  Bias Supply Regulator (VCC, BIAS)
      9. 7.3.9  Bootstrap Voltage and UVLO (CBOOT)
      10. 7.3.10 Spread Spectrum
      11. 7.3.11 Soft Start and Recovery From Dropout
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Foldback
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Automotive Synchronous 6A Buck Regulator at 2.1MHz
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Design 2 – Automotive Synchronous 4A Buck Regulator at 2.1MHz
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.2.2.2  Setting the Output Voltage
          3. 8.2.2.2.3  Choosing the Switching Frequency
          4. 8.2.2.2.4  Inductor Selection
          5. 8.2.2.2.5  Output Capacitor Selection
          6. 8.2.2.2.6  Input Capacitor Selection
          7. 8.2.2.2.7  Bootstrap Capacitor
          8. 8.2.2.2.8  VCC Capacitor
          9. 8.2.2.2.9  BIAS Power Connection
          10. 8.2.2.2.10 Feedforward Network
          11. 8.2.2.2.11 Input Voltage UVLO
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Design 3 – Automotive Synchronous 6A Buck Regulator at 400kHz
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Thermal Design and Layout

For a DC/DC converter to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM63440-Q1 and LM63460-Q1 converter are available in a small 3.5mm × 4mm 22-pin Enhanced HotRod QFN (RYF) package to cover a range of application requirements. The Thermal Information table summarizes the thermal metrics of this package, with related detail provided by the Semiconductor and IC Package Thermal Metrics Application Report.

The 22-pin Enhanced HotRod QFN package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. The exposed pad of the package is thermally connected to the substrate of the LM63440-Q1 or LM63460-Q1 device (ground). This allows a significant improvement in heatsinking, and it becomes imperative that the PCB is designed with thermal lands, thermal vias, and one or more ground planes to complete the heat removal subsystem. The exposed pad of the LM63440-Q1 or LM63460-Q1 is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the IC thermal resistance to a very low value.

Preferably, use a four-layer board with 2oz copper thickness for all layers to provide low impedance, proper shielding and lower thermal resistance. Numerous vias with a 0.3mm diameter connected from the thermal land (and from the area around the PGND1 and PGND2 pins) to the internal and solder-side ground planes are vital to promote heat transfer. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only does this provide a plane for the power-stage currents to flow, but it also represents a thermally conductive path away from the heat-generating devices.