JAJSJO5A October   2022  – October 2023 LM64460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
    2. 6.2 Pinout Design for Clearance and FMEA
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Output Voltage Setpoint (FB)
      3. 8.3.3  Precision Enable and Input Voltage UVLO (EN)
      4. 8.3.4  MODE/SYNC Operation
        1. 8.3.4.1 Level-Dependent MODE/SYNC Control
        2. 8.3.4.2 Pulse-Dependent MODE/SYNC Control
      5. 8.3.5  Clock Locking
      6. 8.3.6  Power-Good Monitor (PGOOD)
      7. 8.3.7  Bias Supply Regulator (VCC, BIAS)
      8. 8.3.8  Bootstrap Voltage and UVLO (CBOOT)
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Overcurrent and Short-Circuit Protection
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Foldback
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – Automotive Synchronous Buck Regulator at 2.1 MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Setting the Output Voltage
          3. 9.2.1.2.3  Choosing the Switching Frequency
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  Bootstrap Capacitor
          8. 9.2.1.2.8  VCC Capacitor
          9. 9.2.1.2.9  BIAS Power Connection
          10. 9.2.1.2.10 Feedforward Network
          11. 9.2.1.2.11 Input Voltage UVLO
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20210623-CA0I-4TT1-B6BK-8PDP7BDX5DBD-low.svg Figure 6-1 22-Pin Enhanced HotRod™ QFNRYF Package(Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CBOOT 1 P High-side driver supply rail. Connect a 100-nF capacitor between SW and CBOOT. An internal bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low.
NC 2 — No internal connection
BIAS 3 P Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high-quality 0.1-µF to 1-µF capacitor from this pin to GND for improved noise immunity. If the output voltage is above 12 V, connect BIAS to GND.
VCC 4 O Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads. Connect a high-quality 1-µF capacitor from VCC to GND.
FB 5 I Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3-V or 5-V output voltage settings. Connect to a feedback divider tap point to set an adjustable output voltage. Do not float or connect to GND.
PGOOD 6 O Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low, VIN > 1 V.
MODE/SYNC 7 I MODE/SYNC controls the mode of operation of the LM64460-Q1. Modes include AUTO mode (automatic PFM / PWM operation), FPWM, and synchronization to an external clock. When synchronized, the clock triggers on rising edge of an external clock signal. Spread spectrum operation is also controlled by this pin. See MODE/SYNC Operation. Do not float this pin.
EN 8 I Enable input and undervoltage lockout (UVLO) programming pin. If the EN voltage is below 0.4 V, the converter is in shutdown mode with all functions disabled. If the EN voltage is greater than 1.263 V (and the VCC voltage is above its UVLO threshold), the converter is active and switching. Use the precision enable function to set an adjustable input voltage UVLO with hysteresis. See Precision Enable and Input Voltage UVLO (EN).
NC 9 — No internal connection
VIN2 10 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. A low-impedance connection must be provided to VIN1.
NC 11 — No internal connection
PGND2 12 G Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
NC 13 — No internal connection
SW1 14 P Switch node of the converter. Connect to the output inductor.
SW2 15
SW3 16
NC 17 — No internal connection
PGND1 18 G Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
NC 19 — No internal connection
VIN1 20 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. A low-impedance connection must be provided to VIN2.
NC 21 — No internal connection
SW4 22 P Switch node of the converter. Connect to the bootstrap capacitor.
GND – G Exposed pad of the package internally connected to ground. The exposed pad must be connected to the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal impedance. See Layout Guidelines.
(1) P = Power, G = Ground, I = Input, O = Output