JAJSVQ2 November   2024 LM644A2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  Output Voltage Selection and Soft Start
      4. 7.3.4  SYNC Allows Clock Synchronization and Mode Selection
      5. 7.3.5  Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Power-Good Output Voltage Monitoring
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage and VCBOOT-UVLO (CB1 and CB2 Pin)
      10. 7.3.10 CONFIG Device Configuration Pin
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery From Dropout
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Hiccup
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  VCC
        8. 8.2.2.8  CFF and RFF Selection
        9. 8.2.2.9  SYNCHRONIZATION AND MODE
        10. 8.2.2.10 External UVLO
        11. 8.2.2.11 Typical Thermal Performance
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 SYNC Allows Clock Synchronization and Mode Selection

The SYNC pin can be used to select forced pulse width modulation (FPWM) or pulse frequency modulation (PFM). In FPWM the switching frequency remains constant at lighter output currents. In PFM the low-side FET is turned off when the inductor current goes negative and the frequency is reduced to improve efficiency under light-load conditions. Connect SYNC to AGND to enable PFM. Connect SYNC to VCC to operate the LM644A2-Q1 in FPWM mode with continuous conduction at light loads.

The SYNC pin can also be used to synchronize the internal oscillator to an external clock. When synchronized to an external clock the LM644A2-Q1 operates in FPWM. The internal oscillator can be synchronized to a positive edge into the SYNC pin. The coupled edge voltage at the SYNC pin must exceed the SYNC amplitude threshold of VSYNCDH to trip the internal synchronization pulse detector. The minimum SYNC rising pulse and falling pulse durations must be longer than tPULSE_H and tPULSE_L respectively. The LM644A2-Q1 switching action can be synchronized to an external clock from 200kHz to 2.2MHz. When synchronizing to an external clock, the RT pin must be used to set the internal frequency to a value close to that of the external clock. This action prevents large frequency changes in the event of loss of synchronization. This action is also used to set the slope compensation for secondary devices.

In single-output two-phase operation, the PG2/SYNC-OUT terminal of the primary can be left floating as clock information is shared internally.

In single-output four-phase operation, the PG2/SYNC-OUT terminal of the primary must be connected to the SYNC pin of the secondary to clock all four phases 90 degrees out of phase.

In single-output six-phase operation, the PG2/SYNC-OUT terminal of the primary must be connected to the SYNC pin of the secondary device. The PG2/SYNC-OUT terminal of the secondary must be connected to the SYNC pin of the tertiary device. In this way, the devices operate all six phases 60 degrees out of phase.

LM644A2-Q1 Typical Implementation Allowing Synchronization Using the SYNC/MODE PinFigure 7-4 Typical Implementation Allowing Synchronization Using the SYNC/MODE Pin
LM644A2-Q1 Typical SYNC/MODE Waveform
This image shows the conditions needed for detection of a synchronization signal.
Figure 7-5 Typical SYNC/MODE Waveform