JAJSVQ2 November   2024 LM644A2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  Output Voltage Selection and Soft Start
      4. 7.3.4  SYNC Allows Clock Synchronization and Mode Selection
      5. 7.3.5  Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Power-Good Output Voltage Monitoring
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage and VCBOOT-UVLO (CB1 and CB2 Pin)
      10. 7.3.10 CONFIG Device Configuration Pin
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery From Dropout
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Hiccup
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  VCC
        8. 8.2.2.8  CFF and RFF Selection
        9. 8.2.2.9  SYNCHRONIZATION AND MODE
        10. 8.2.2.10 External UVLO
        11. 8.2.2.11 Typical Thermal Performance
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

VGB package, 24-pin VQFN-FCRLF with wettable flanks

LM644A2-Q1 Dual Output (Top View) Figure 5-1 Dual Output (Top View)
LM644A2-Q1 Single Output Primary (Top View) Figure 5-2 Single Output Primary (Top View)
LM644A2-Q1 Single Output Secondary (Top View) Figure 5-3 Single Output Secondary (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
DUAL OUTPUT SINGLE OUTPUT
1 VIN2 VIN2 I Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND2. Low impedance connection must be provided to VIN1.
2 BOOT2 BOOT2 I/O Channel 2 high-side driver upper supply rail. Connect a 100nF capacitor between SW2 and BOOT2. An internal diode charges the capacitor while SW2 is low.
3 SW2 SW2 P Channel 2 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor.
4 PGND3 PGND3 G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1, PGND2 and exposed pad.
5 SW1 SW1 P Channel 1 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor.
6 BOOT1 BOOT1 I/O Channel 1 High-side driver upper supply rail. Connect a 100nF capacitor between SW1 and BOOT1. An internal diode charges the capacitor while SW1 is low.
7 VIN1 VIN1 I Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND1. Low impedance connection must be provided to VIN2.
8 SERIES CAP1 SERIES CAP1 NC This pin is not internally connected. The pin is provided for pin compatibility with LMQ644xx series where this pin is connected to mid-point of two series capacitors between pins VIN1 and PGND1. This pin can be left floating, or can be connected to the mid-point of additional bypass capacitors in series configuration if required for the end application.
9 PGND1 PGND1 G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND2 and PGND3. Connect a high quality bypass capacitors from this pin to VIN1.
10 SYNC SYNC I Multi-function pin. SYNC selects forced pulse width modulation (FPWM) or Diode Emulation mode. Connect SYNC to AGND to enable diode emulation mode. Connect SYNC to VCC to operate the LM644A2-Q1 in FPWM mode with continuous conduction at light loads. SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock. When used as a secondary device in single output configuration, the SYNC pin is connected to SYNC_OUT of the primary for clock timing.
11 PG1 MODE O Dual function pin. An open drain output that transitions low if VOSNS1 is outside a specified regulation window in dual output and single output primary configuration. In single output secondary mode configuration, this behaves as a mode pin to select between forced PWM (FPWM) mode and Diode Emulation Mode (DEM). Connect MODE of single output secondary to SYNC pin of single output primary to place them in the same mode of operation. For FPWM, connect MODE to VCC through a 10 kOhm resistor. For DEM connect to ground.
12 EN1 EN1 I An active high input LM644A2-Q1 (VOH > 1.375V) enables Output 1 in dual output operation. When in single output operation, an active high input enables all phases in the system. When disabled, the LM644A2-Q1 is in shutdown mode. EN1 must never be floating.
13 BIAS and VOSNS1 BIAS and VOSNS1 I Output voltage sense and input to internal voltage regulator. Connect to non-switching side of the inductor. Connect an optional high quality 0.1μF capacitor from this pin to AGND for best performance.
14 FB1 FB1 I Feedback input to channel 1 of the LM644A2-Q1 in dual output operation and feedback input to all channels in single output operation. Connect FB1 to VCC through a 10 kOhm resistor for a 5V output or connect FB1 to AGND for a 3.3V output. A resistive divider from the non-switching side of the inductor to FB1 sets the output voltage level between 0.8V and 20V. The regulation threshold at FB1 is 0.8V. For lower output voltages use at least a 10kOhm for the top of the resistor divider.
15 VCC VCC O Internal regulator output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high quality 1μF capacitor from this pin to AGND.
16 AGND AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
17 RT RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz.
18 FB2 SS I Dual function pin. When in dual output operation, the pin functions as FB2, feedback input to channel 2 of the LM644A2-Q1. Connect FB2 to VCC through a 10 kOhm resistor for a 5V output or connect FB2 to AGND for a 3.3V output. A resistive divider from the non-switching side of the inductor to FB2 sets the output voltage level between 0.8V and 20V. For lower output voltages use at least a 10kOhm for the top of the resistor divider. When in single output mode, the pin functions as SS. An external capacitor must be placed from SS to AGND for external soft-start of the output. Connect the SS pins of primary and secondaries for fault communication between devices.
19 VOSNS2 COMP I Dual function pin. In dual output operation, the pin functions as VOSNS2 for the fixed 3.3V and 5V and adjustable output conditions. In single output operation, the pin is the output of the internal error amplifier.
20 EN2 EN2 I An active high input (VOH > 1.375V) enables Output 2 in dual output operation. When in single output mode, EN2 of all LM644A2-Q1 must be connected together. An active high input enables all secondary phases in the system. When disabled, only one channel in the primary LM644A2-Q1 is active while all remaining phases are in shutdown mode. EN2 must never be floating.
21 CONFIG CONFIG I Single or Dual output selection. Connect specific resistor values to the pin (refer to Table 7-3) to select number of phases, primary and secondary and dither options.
22 PG2 SYNC_ OUT O Dual function pin. In dual output operation, this pin behaves as PG2, an open drain output that transitions low if VOSNS2 is outside a specified regulation window. In single output mode, the pin functions as SYNC_OUT and provides clock information from primary to secondary.
23 PGND2 PGND2 G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1, PGND3 and PGND4. Connect a high quality bypass capacitors from this pin to VIN2.
24 SERIES CAP2 SERIES CAP2 NC This pin is not internally connected. The pin is provided for pin compatibility with LMQ644xx series where this pin is connected to mid-point of two series capacitors between pins VIN1 and PGND1. This pin can be left floating, or can be connected to the mid-point of additional bypass capacitors in series configuration if required for the end application.
25 PGND4 PGND4 G Power ground and heat sink connection. Solder directly to system ground plane. Low impedance connection must be provided to PGND1, PGND2 and PGND3.
(1) I = input, O = output, P = power, G = ground