JAJSVQ2 November   2024 LM644A2-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  Output Voltage Selection and Soft Start
      4. 7.3.4  SYNC Allows Clock Synchronization and Mode Selection
      5. 7.3.5  Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Power-Good Output Voltage Monitoring
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage and VCBOOT-UVLO (CB1 and CB2 Pin)
      10. 7.3.10 CONFIG Device Configuration Pin
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery From Dropout
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Hiccup
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  VCC
        8. 8.2.2.8  CFF and RFF Selection
        9. 8.2.2.9  SYNCHRONIZATION AND MODE
        10. 8.2.2.10 External UVLO
        11. 8.2.2.11 Typical Thermal Performance
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Enable EN Pin and Use as VIN UVLO

Apply a voltage less than 0.25V to the EN1 pin to put the LM644A2-Q1 into shutdown mode. In shutdown mode, the quiescent current drops to 0.5µA (typical). Above this voltage but below the lower EN threshold, VCC is active but switching on SW1 and SW2 remains inactive. After EN1 is above VEN, the SW1 becomes active. EN2 controls switching on the second output SW2. In dual output configuration EN2 can be used to independently turn off the second output voltage, but does not control entering shutdown mode. In single-output multi-phase configuration EN1 on primaries and secondaries must be tied together. In single output configuration EN1 must not be used to disable the secondary devices for phase shedding. EN2 of the primary and secondaries must be tied together and can be used to shutdown the secondary phases. The very high efficiency of the device in PFM operation eliminates the need to phase shed in most designs as phase of the secondaries is controlled even under PFM operation.

The EN terminals cannot be left floating. The simplest way to enable the operation is to connect the EN pins to VIN. This action allows the self-start-up of the device when VIN drives the internal VCC above the UVLO level. However, many applications benefit from employing an enable divider string, which establishes a precision input undervoltage lockout (UVLO). The precision UVLO can be used for the following:

  • Sequencing
  • Preventing the device from retriggering when used with long input cables
  • Reducing the occurrence of deep discharge of a battery power source
Note that EN thresholds are accurate. The rising enable threshold has 10% tolerance. Hysteresis is enough to prevent retriggering upon shutdown of the load (approximately 38%). The external logic output of another IC can also be used to drive the EN terminals, allowing system power sequencing.

LM644A2-Q1 VIN UVLO Using the EN PinFigure 7-2 VIN UVLO Using the EN Pin

Resistor values can be calculated using the following equations:

Equation 1. RENB=RENT×VEN(R) VIN(on)-VEN(R) 
Equation 2. VOFF=VIN(on)×1-VEN(H)

where

  • VON = VIN turn-on voltage
  • VOFF = VIN turn-off voltage