The PCB layout of any DC/DC converter is critical to the excellent performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck converter, the most EMI-critical PCB feature is the loop formed by the input capacitor or capacitors and power ground. This loop is shown in Figure 8-70. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. Excessive transient voltages can disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short while keeping the loop area as small as possible to reduce the parasitic inductance. Figure 8-71 shows a recommended layout for the critical components of the LM644A2-Q1 circuit.

• Place the input capacitor or capacitors as close as possible to the input pin pairs: VIN1 to PGND1 and VIN2 to PGND2. Place the small capacitors closest. Each pair of pins are adjacent, simplifying the input capacitor placement. With the QFN package, there are two VIN/PGND pairs on either side of the package. This provides a symmetrical layout and helps minimize switching noise and EMI generation. Use a wide VIN plane on a mid-layer to connect both of the VIN pairs together to the input supply. Route symmetrically from the supply to each VIN pin to best use the benefits of the symmetric pinout.
• Place the bypass capacitor for VCC close to the VCC pin and AGND pin: This capacitor must be routed with short, wide traces to the VCC and AGND pins.
• Place the CBOOT capacitors as close as possible to the device with short, wide traces to the CBOOT and SW pins: Make sure to route the SW connection with a short wide trace to handle the current, but not longer than necessary to avoid generating common mode noise.
• Place the feedback divider as close as possible to the FB pin of the device: Place R_FBB, R_FBT, C_FF if used, and R_FF if used, physically close to the device. The connections to FB and AGND through R_FBB must be short and close to those pins on the device. The connection to V_OUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
• Make layer 2 of the PCB a ground plane: This plane acts as a noise shield and as a heat dissipation path. Using layer 2 reduces the enclosed area in the input circulating current in the input loop, reducing inductance.
• Provide wide paths for V_IN, V_OUT, and GND: These paths must be as wide and direct as possible to reduce any voltage drops on the input or output paths of the converter to maximize efficiency.
• Provide enough PCB area for proper heat sinking: Enough copper area must be used to make sure a low R_θJA, considering maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note that the package of this device dissipates heat through all pins. Wide traces can be used for all pins except where noise considerations dictate minimization of area.
• Keep the switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

Figure 8-70 Input Current Loop