JAJSVQ2 November   2024 LM644A2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  Output Voltage Selection and Soft Start
      4. 7.3.4  SYNC Allows Clock Synchronization and Mode Selection
      5. 7.3.5  Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Power-Good Output Voltage Monitoring
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage and VCBOOT-UVLO (CB1 and CB2 Pin)
      10. 7.3.10 CONFIG Device Configuration Pin
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery From Dropout
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Hiccup
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  VCC
        8. 8.2.2.8  CFF and RFF Selection
        9. 8.2.2.9  SYNCHRONIZATION AND MODE
        10. 8.2.2.10 External UVLO
        11. 8.2.2.11 Typical Thermal Performance
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 13.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN-DT3p3) VIN quiescent current, dual output mode, BIAS = 3.3V Non-switching, VEN = 2V, VBIAS = VVOSNS1 = 3.3V + 10%, VVOSNS2 = 5V + 10% 7 30 µA
IQ(VIN-ST5p0) VIN quiescent current, single output mode Non-switching, VEN = 2V, VBIAS = VVOSNS1 = 5V + 10% 29 55 µA
IQ(VIN-ST3p3) VIN quiescent current, single output mode Non-switching, VEN = 2V, VBIAS = VVOSNS1 = 3.3V + 10% 18 43 µA
ISD(VIN) VIN shutdown supply current VEN = 0V, +25c degrees results only, all corners (n,w,s) 0.5 8 µA
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.5 3.80 V
VINUVLO(F) VIN UVLO falling threshold VIN falling 2.5 V
VINUVLO(H) VIN UVLO hysteresis 0.75 1 1.25 V
ENABLE
VEN(R) EN1/2 voltage rising threshold EN1/2 rising, enable switching 1.125 1.25 1.375 V
VEN(F) EN1/2 voltage falling threshold EN1/2 falling, disable switching 0.8 0.9 1.0 V
VEN(H) EN1/2 voltage hysteresis 0.25 0.325 0.55 V
VEN(W) EN1/2 voltage wake-up threshold 0.4 V
IEN EN1/2 pin sourcing current post EN rising threshold VEN1/2 = VIN = 13.5V 1 400 nA
INTERNAL LDO
VVCC Internal LDO output voltage VBIAS ≥ 3.4V, IVCC ≤ 100mA 2.7 3.1 3.7 V
IVCC Internal LDO short-circuit current limit VIN = 13.5V 100 360 880 mA
VVCC(UVLO-R) VCC UVLO rising threshold for startup 3.3 3.5 3.75 V
VVCC(UVLO-F) VCC UVLO falling threshold for shutdown 2.5 3 V
REFERENCE VOLTAGE
VFB1/2 Dual Output FB voltages in adjustable output configuration 788 800 812 mV
VFB1_so Single Output mode FB voltage in adjustable output configuration 788 800 812 mV
IFB1/2(LKG) FB input leakage current in dual output configuration VFB1/2 = 0.8V 10 250 nA
IFB1_so(LKG) FB input leakage current in single output configuration VFB = 0.8V 10 250 nA
FBSel-5v0 Voltage threshold for fixed 5.0V setting VCC-0.5 V
FBSel-3v0 Resistor for fixed 3.3V setting 300 Ω
FBSel-ext Minimum Thevenin Equivalent resistance of external FB divider option to select adjustable output voltage. 4 kΩ
ERROR AMPLIFIER
gm-S1 EA transconductance - single output mode VFB1 = VCOMP 625 1000 1300 µS
ICOMP(src) EA source current - single output mode VCOMP = 1V, VFB1 = 0.4V 100 200 400 µA
ICOMP(sink) EA sink current - single output mode VCOMP = 1V, VFB1 = 0.8V 100 200 500 µA
SWITCHING FREQUENCY
fSW1(FPWM) Switching frequency, FCCM operation RRT = 7.15kΩ to AGND 1.9 2.1 2.3 MHz
fSW2(FPWM) Switching frequency, FCCM operation RRT = 39.2kΩ to AGND  360 410 450 kHz
fADJ(FCCM) Adjustable switching frequency range RRT resistor from 6.81kΩ to 158kΩ to AGND 0.1 2.2 MHz
fSS(int) Spread Spectrum switching frequency range RRT = 7.15 kΩ, RCONFIG= 73.2k Ω +-10%
SYNCHRONIZATION
VIH(sync) SYNCIN high-level threshold 1.35 1.6 V
VIL(sync) SYNCIN low-level threshold 0.65 0.95 V
VOH(sync) Sync output high voltage min 10mA load 1.6 2.6 V
VOL(sync) Sync output low voltage max 10mA load 0.35 0.68 V
fSYNC-2p1 Frequency sync range around 2.1MHz RRT = 7.15kΩ to AGND 1.7 2.1 2.4 MHz
fSYNC-0p4 Frequency sync range around 400kHz RRT = 39.2kΩ to AGND 320 400 480 kHz
tSYNC(min) Pulse width of external synchronization signal above VIH(sync) 100 ns
tSYNC(max) Pulse width of low external synchronization signal below VIL(sync) 100 ns
tSYNC-SW(delay) Delay from SYNC rising edge to SW rising edge - single output mode - secondary 120 ns
STARTUP
tSS(R) Internal fixed soft-start time - dual output mode From VVOSNS1/2= 0% (first SW pulse) to VVOSNS1/2 = 90% 2.7 4.5 7 ms
tSS_Lockout(R) Time from first SW1/2 pulse to enable FPWM mode if output not in regulation - dual output mode 7 13 32 ms
ISS(R) Soft-start charge current - single output mode VSS = 0V 15 20 25 µA
RSS(F) Soft-start discharge resistance - single output mode 10 27 Ω
tEN EN1 (Single output mode) or EN1/EN2 (whichever first in dual output mode) HIGH to start of switching delay 600 900 µs
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance VBOOT-SW = 3.3V, IOUT = 1A 37 75 mΩ
RDSON(LS) Low-side MOSFET on-resistance VVCC = 3.3V, IOUT = 1A 23.9 50 mΩ
tON(min) Minimum ON pulse width VIN = 20V, IOUT = 2A 50 65 ns
tON(max) Maximum ON pulse width (dual output, single output primary) RRT = 7.15kΩ 5 8 12 µs
tON(max) Maximum ON pulse width (single output secondary) RRT = 7.15kΩ 16 25 µs
tOFF(min) Minimum OFF pulse width VIN = 4V 80 110 ns
BOOT CIRCUIT
OVERCURRENT PROTECTION
IHS(OC3) High-side peak current limit LM644A2 Peak current limit on HS FET when Duty Cycle approaches 0%  8.99 11 13.9 A
ILS(OC3) Low-side valley current limit LM644A2 Valley current limit on LS FET 6.2 7.7 9.27 A
ILS3(NOC) Low-side negative current limit LM644A2 Sinking current limit on LS FET 5 A
ILPEAK3(min-0) Min peak inductor current at minimum duty cycle LM644A2 VVCC = 3.3V, tpulse ≤ 100ns 1.5 A
ILPEAK3(min-100) Min peak inductor current at maximum duty cycle LM644A2 VVCC = 3.3V, tpulse ≥ 1µs 0.4 A
VHiccup-FB Hiccup threshold on FB pin - dual output mode, adjustable output option LS FET On-time > 165ns .25 0.3 0.35 V
tHiccup-1 Wait time before entering Hiccup - single and dual output mode 126 128 130 Curent Limit cycles
tHiccup-2 Hiccup time before re-start 50 88 ms
POWER GOOD
VPGTH-1 Power-Good threshold (PG1/2) PGOOD low, VVOSNS1/2 rising 93% 95% 97%
VPGTH-2 Power-Good threshold (PG1/2) PGOOD high, VVOSNS1/2 falling  92% 94% 96%
VPGTH-3 Power-Good threshold (PG1/2) PGOOD high, VVOSNS1/2 rising 105% 107% 110%
VPGTH-4 Power-Good threshold (PG1/2) PGOOD low, VVOSNS1/2 falling 104% 106% 109%
tPGOOD(R) PG1/2 delay from VVOSNS1/2 valid to PGOOD high during start-up VVOSNS1/2 = 3.3V 2.3 ms
tPGOOD(F) PG1/2 delay from VVOSNS1/2 invalid to PGOOD low  VVOSNS1/2 = 3.3V 45 µs
IPG(LKG) PG1/2 pin Leakage current when open drain output is high VPG = 3.3V 0.1 µA
VPG-D(LOW) PG pin output low-level voltage for both channels  IPG = 1mA, VEN = 0V. 400 mV
RPG-1 Pull Down MOSFET Resistance IPG = 1mA, VEN = 3.3V. 30 90 Ω
VIN(PG_VALID) Min VIN for valid PG output Pull up resistance on PG - RPG = 10kΩ, Voltage Pull up on PG - VPULLUP_PG = 3V, VPG-D(LOW) = 0.4V 0.45 1.2 V
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold Temperature rising 168 °C
TJ(HYS) Thermal shutdown hysteresis 10 °C