JAJSOR6 September 2024 LM706A0-Q1
PRODUCTION DATA
The LM706A0-Q1 outputs can be independently configured for one of the three fixed output voltages with no external feedback resistors, or adjusted to the desired voltage using an external resistor divider network. The output can be configured as a 3.3V output by connecting the FB pin to VDDA, a 5V output by connecting FB through a 24.9kΩ resistor to VDDA, or 12V by connecting the FB pin through a 49.9kΩ resistor to VDDA. With the output voltage selection, the VCC bias regulator output level is selected as well as shown in Table 6-1. The configuration settings are latched and cannot be changed until the input voltage to the LM706A0-Q1 is recycled.
FB Pin | Output Voltage | VCC Voltage |
---|---|---|
Short to VDDA | 3.3V | 5V |
24.9kΩ to VDDA | 5.0V | 5V |
49.9kΩ to VDDA | 12V | 8V |
Resistor divider to VOUT | 0.8V to 55V | 8V |
Alternatively, the output voltage can be set using external resistive dividers from the output to the FB pin. The output voltage adjustment range is between 0.8V and 36V. The voltage reference setpoint is 0.8V (VREF). Use Equation 5 to calculate the upper and lower feedback resistors, designated RFB1 and RFB2 respectively.
The recommended starting value for RFB2 is between 10kΩ and 20kΩ.
If a low IQ mode is required, be careful when selecting the external resistors. The extra current drawn from the external divider is added to the LM706A0-Q1 IQ-SLEEP current. The divider current reflected to VIN is divided down by the ratio of VOUT/VIN.