JAJSJX9A September   2023  – June 2024 LM70840-Q1 , LM70860-Q1 , LM70880-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
      3. 7.3.3  Enable (EN)
      4. 7.3.4  Power-Good Monitor (PG)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Dual Random Spread Spectrum (DRSS)
      7. 7.3.7  Soft Start
      8. 7.3.8  Output Voltage Setpoint (FB)
      9. 7.3.9  Minimum Controllable On-Time
      10. 7.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 7.3.11 Slope Compensation
      12. 7.3.12 Shunt Current Sensing
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 Device Configuration (CONFIG)
      15. 7.3.15 Single-Output Dual-phase Operation
      16. 7.3.16 Pulse Frequency Modulation (PFM) / Synchronization
      17. 7.3.17 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Sleep Mode
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High Efficiency, Wide Input, 400-kHz Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3 Buck Inductor
          4. 8.2.1.2.4 Current-Sense Resistance
          5. 8.2.1.2.5 Output Capacitors
          6. 8.2.1.2.6 Input Capacitors
          7. 8.2.1.2.7 Frequency Set Resistor
          8. 8.2.1.2.8 Feedback Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High Efficiency 48V to 12V 400kHz Synchronous Buck Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Thermal Design and Layout
      3. 8.4.3 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RRX|29
サーマルパッド・メカニカル・データ
Input Capacitors

A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the input ripple voltage. As mentioned earlier, dual-channel interleaved operation significantly reduces the input ripple amplitude. In general, the ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency.

  1. Select the input capacitors with sufficient voltage and RMS ripple current ratings.
  2. Use Equation 39 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle operating point of 50%.
    Equation 39. I C I N ( r m s )   =   I O U T × D × ( 1 - D )   = 8 A   ×   0.5   ×   ( 1 - 0.5 ) = 4 A  
  3. Use Equation 40 to find the required input capacitance.
    Equation 40. C I N     D × 1 - D × I O U T F S W × ( Δ V I N - R E S R × I O U T ) = 0.5 × 1 - 0.5 × 8 A 400 k H z   × 480 m V - 2 m Ω   ×   8 A =   10.8 µ F

    where

    • ΔVIN is the input peak-to-peak ripple voltage specification.
    • RESR is the input capacitor ESR.
  4. Recognizing the voltage coefficient of ceramic capacitors, select two 4.7µF, 100V, X7R, 1210 ceramic input capacitors. Place these capacitors adjacent to the VIN and PGND pins.
  5. Use a 10nF, 100V, X7R, 0603 ceramic capacitor near the VIN and PGND pins to supply the high di/dt current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF) and low effective impedance above 100MHz. The result is lower power loop parasitic inductance, thus minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature. Refer to Section 8.4.1 for more detail.