JAJSJX9A September   2023  – June 2024 LM70840-Q1 , LM70860-Q1 , LM70880-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
      3. 7.3.3  Enable (EN)
      4. 7.3.4  Power-Good Monitor (PG)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Dual Random Spread Spectrum (DRSS)
      7. 7.3.7  Soft Start
      8. 7.3.8  Output Voltage Setpoint (FB)
      9. 7.3.9  Minimum Controllable On-Time
      10. 7.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 7.3.11 Slope Compensation
      12. 7.3.12 Shunt Current Sensing
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 Device Configuration (CONFIG)
      15. 7.3.15 Single-Output Dual-phase Operation
      16. 7.3.16 Pulse Frequency Modulation (PFM) / Synchronization
      17. 7.3.17 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Sleep Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High Efficiency, Wide Input, 400-kHz Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3 Buck Inductor
          4. 8.2.1.2.4 Current-Sense Resistance
          5. 8.2.1.2.5 Output Capacitors
          6. 8.2.1.2.6 Input Capacitors
          7. 8.2.1.2.7 Frequency Set Resistor
          8. 8.2.1.2.8 Feedback Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High Efficiency 48V to 12V 400kHz Synchronous Buck Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Thermal Design and Layout
      3. 8.4.3 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
  • RRX|29
サーマルパッド・メカニカル・データ

7.4.2 Standby Mode

The internal bias LDO has a lower enable threshold than the switching regulator. When VEN is above 0.55V (typical) and below the precision enable threshold of 1V (typical), the internal LDO is on and regulating. The precision enable circuitry is turned on if the LDO output is above the bias rail UV threshold. The switching and output voltage regulation are disabled in standby mode.