The LM708x0-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation (DEM), the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss during light load operation. Note: configuring the device for DEM has an effect of slower response to load transients during light load operation.

The diode emulation feature is configured with the PFM / SYNCIN pin. To enable diode emulation and thus achieve discontinuous conduction mode (DCM) operation at light loads, connect PFM / SYNCIN to VDDA. Note that diode emulation is automatically engaged to prevent reverse current flow during a prebias start-up in PFM. During start up, when the output voltage approaches the regulation set point a gradual change from DCM to CCM occurs, preventing the output voltage overshoot.

If forced pulse-width modulation (FPWM) or continuous conduction mode (CCM) operation is desired, tie PFM / SYNCIN to AGND. Note that the LM708x0-Q1 transitions from PFM to FPWM mode whenever LM708x0-Q1 is reset. The time to transition to FPWM operation is dependent on the output load current. In a typical application, the transition from PFM to FPWM operation occurs in less than 1ms if the output current is greater than 100mA. Similarly, for the output currents of around 1mA, the transition generally occurs in tens of milliseconds.

To synchronize the LM708x0-Q1 to an external source, apply a logic-level clock (greater than 1.17V) to the PFM / SYNCIN pin. The LM708x0-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.2MHz. If there is an RT resistor and a synchronization signal, the LM708x0-Q1 ignores the RT resistor and synchronizes to the external clock. Under low V_IN conditions when the minimum off-time is reached, the synchronization signal is ignored, allowing the switching frequency to be reduced to maintain output voltage regulation.

When in FPWM mode, the time for the LM708x0-Q1 to be synchronized to an external clock frequency is approximately 100μs. If an external clock is applied after startup while operating in PFM mode, the time to synchronize the switching frequency is dependent on the load. In a typical application, switch synchronization and FPWM operation occurs in less than 1ms if the output current exceeds 100mA. Similarly, for the output currents of around 1mA, the synchronization generally occurs in tens of milliseconds.