SNOS926F May 1999 – September 2014 LM7372
PRODUCTION DATA.
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The LM7372 is fabricated on a high voltage, high speed process. Using high supply voltages ensures adequate headroom to give low distortion with large signal swings. In Figure 24, a single 24 V supply is used. To maximize the output dynamic range the non-inverting inputs are biased to half supply voltage by the resistive divider R1, R2. The input signals are AC coupled and the coupling capacitors (C1, C2) can be scaled with the bias resistors (R3, R4) to form a high pass filter if unwanted coupling from the POTS signal occurs.
Supply decoupling is important at both low and high frequencies. The 10µF Tantalum and 0.1µF Ceramic capacitors should be connected close to the supply Pin 14. Note that the V− pin (pin 6), and the PCB area associated with the heatsink (Pins 1,8,9 & 16) are at the same potential. Any layout should avoid running input signal leads close to this ground plane, or unwanted coupling of high frequency supply currents may generate distortion products.
Although this application shows a single supply, conversion to a split supply is straightforward. The half supply resistive divider network is eliminated and the bias resistors at the non-inverting inputs are returned to ground. For example, see Figure 23 where the pin numbers in Figure 23 are given for SO PowerPAD package, whereas those in Single Supply Application (16-Pin SOIC) are for the SOIC package. With a split supply, note that the ground plane and the heatsink copper must be separate and are at different potentials, with the heatsink (pin 4 of the SO PowerPAD, pins 6,1,8,9 and 16 of the SOIC) now at a negative potential (V−).
In either configuration, the area under the input pins should be kept clear of copper (whether ground plane copper or heatsink copper) to avoid parasitic coupling to the inputs.
The LM7372 is stable with non inverting closed loop gains as low as +2. Typical of any voltage feedback operational amplifier, as the closed loop gain of the LM7372 is increased, there is a corresponding reduction in the closed loop signal bandwidth. For low distortion performance it is recommended to keep the closed loop bandwidth at least 10X the highest signal frequency. This is because there is less loop gain (the difference between the open loop gain and the closed loop gain) available at higher frequencies to reduce harmonic distortion terms.