JAJSHW4 September   2019 LM74202-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      12V での ISO16750-2 ロードダンプ・パルス 5b 性能
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1      Absolute Maximum Ratings
    2. 6.2      ESD Ratings
    3. 6.3      Recommended Operating Conditions
    4. Table 1. Thermal Information
    5. 6.4      Electrical Characteristics
    6. 6.5      Timing Requirements
    7. 6.6      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Reverse Battery Protection
      4. 8.3.4 Hot Plug-In and In-Rush Current Control
      5. 8.3.5 Overload and Short Circuit Protection
        1. 8.3.5.1 Overload Protection
          1. 8.3.5.1.1 Active Current Limiting
          2. 8.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 Start-Up With Short-Circuit On Output
        3. 8.3.5.3 FAULT Response
          1. 8.3.5.3.1 Look Ahead Overload Current Fault Indicator
        4. 8.3.5.4 Current Monitoring
        5. 8.3.5.5 IN, OUT, RTN and GND Pins
        6. 8.3.5.6 Thermal Shutdown
        7. 8.3.5.7 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step by Step Design Procedure
        2. 9.2.2.2 Setting Undervoltage Lockout and Overvoltage Set Point for Operating Voltage Range
        3. 9.2.2.3 Programming the Current-Limit Threshold—R(ILIM) Selection
        4. 9.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 9.2.2.5 Limiting the Inrush Current
          1. 9.2.2.5.1 Selection of Input TVS for Transient Protection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
UVLO INPUT
UVLO Turn On Delay UVLO_tON(dly) UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV, C(dvdt) = Open 80 µs
UVLO_tON(dly) UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 80+14.5 x C(dvdt)
UVLO Turn-Off delay UVLO_toff(dly) UVLO↓ (100mV below V(UVLOF)) to FLT ↓ 9 µs
SHUTDOWN INPUT
SHUTDOWN Exit delay SHDN_ton(dly) SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 350+14.5 x C(dvdt) µs
SHDN_ton(dly) SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV, C(dvdt)= Open 355
SHUTDOWN Entry delay SHDN_toff(dly) SHDN ↓ (below V(SHUTF) to FLT ↓ 10 µs
OVP INPUT
OVP Exit delay tOVP(dly) OVP ↓(20mV below V(OVPF)) to V(OUT) = 100mV 205 µs
OVP Disable delay tOVP(dly) OVP↑ (20mV above V(OVPR)) to FLT ↓ 2 µs
CURRENT LIMIT
Fast-Trip Comparator Delay tFASTTRIP(dly) I(OUT) = 1.5x I(FASTRIP) 170 ns
REVERSE CURRENT BLOCKING COMPARATOR
RCB comparator delay tREV(dly) (V(IN)-V(OUT)) ↓ (100mV overdrive below V(REVTH))  to internal FET OFF 1.29 µs
(V(IN)-V(OUT)) ↓ (10mV overdrive below V(REVTH)) to FLT ↓ 40 µs
tFWD(dly) (V(IN)-V(OUT)) ↑ (10mV overdrive above V(FWDTH)) to FLT ↑ 60 µs
THERMAL SHUTDOWN
Retry Delay in TSD tretry 540 ms
OUTPUT RAMP TIME
Output Ramp Time tdVdT SHDN↑ to V(OUT) = V(IN) 1.6 ms
SHDN↑ to V(OUT) = V(IN), with C(dVdT) = 47nF 10 ms
FAULT FLAG
FLT assertion delay in circuit breaker mode tCB(dly) MODE = OPEN,Delay from I(out)>I(lim) to FLT ↓(and internal FET turned off) 4 ms
Retry Delay in circuit breaker mode tCBretry(dly) MODE= OPEN,  C(dVdT) = Open. I(out)>I(lim). Delay from FLT ↓ to V(dVdT) = 50mV (Rising) 540 ms
PGOOD delay time tPGOODR Delay for rising FLT  edge 1.8 ms
tPGOODF Delay for falling FLT  edge 900 µs