JAJSMX1B September   2021  – March 2022 LM74720-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dual Gate Control (GATE, PD)
        1. 8.3.1.1 Reverse Battery Protection (A, C, GATE)
        2. 8.3.1.2 Load Disconnect Switch Control (PD)
      2. 8.3.2 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      3. 8.3.3 Boost Regulator
    4. 8.4 Device Functional Mode (Shutdown Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
        1. 9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 9.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Boost Converter Components (C2, C3, L1)
        3. 9.2.3.3 Input and Output Capacitance
        4. 9.2.3.4 Hold-Up Capacitance
        5. 9.2.3.5 Overvoltage Protection and Battery Monitor
        6. 9.2.3.6 MOSFET Selection: Blocking MOSFET Q1
        7. 9.2.3.7 MOSFET Selection: Load Disconnect MOSFET Q2
        8. 9.2.3.8 TVS Selection
      4. 9.2.4 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 TVS Selection for 12-V Battery Systems
    3. 10.3 TVS Selection for 24-V Battery Systems
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRR|12
サーマルパッド・メカニカル・データ
発注情報

8.3.1.1 Reverse Battery Protection (A, C, GATE)

A, C, GATE comprises of Ideal Diode stage. Connect the Source of the external MOSFET to A, Drain to C and Gate to GATE pin. The LM74720-Q1 has integrated reverse input protection down to –65 V.

In LM74720-Q1, the voltage drop across the MOSFET is continuously monitored between the A and C pins, and the GATE to A voltage is adjusted as needed to regulate the forward voltage drop at 17 mV (typical) for LM74720-Q1. This closed loop regulation scheme enables graceful turn-off of the MOSFET during a reverse current event and ensures zero DC reverse current flow. This scheme ensures robust performance during slow input voltage ramp down tests. Along with the linear regulation amplifier scheme, the LM74720-Q1 also integrates a fast reverse voltage comparator. When the voltage drop across A and C reaches V(AC_REV) threshold, then the GATE goes low within 0.5 µs (typical). This fast reverse voltage comparator scheme ensures robust performance during fast input voltage ramp down tests such as input micro-shorts. The external MOSFET is turned back ON when the voltage across A and C hits V(AC_FWD) threshold within 1.9 µs (typical). For ideal diode only designs, connect LM74720-Q1 as shown in Figure 8-1.

GUID-20210831-SS0I-4VKW-ZRZZ-VQCCRHFCQNMH-low.gifFigure 8-1 Configuring LM74720-Q1 for Ideal Diode Only