JAJSIL9A February   2020  – July 2020 LM76005-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current-Mode Control
      2. 7.3.2  Light Load Operation Modes — PFM and FPWM
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (EN Pin) and UVLO
      5. 7.3.5  Internal LDO, VCC UVLO, and Bias Input
      6. 7.3.6  Soft Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Adjustable Switching Frequency (RT) and Frequency Synchronization
      8. 7.3.8  Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Bootstrap Voltage and VBOOT UVLO (BOOT Pin)
      10. 7.3.10 Power Good and Overvoltage Protection (PGOOD)
      11. 7.3.11 Overcurrent and Short-Circuit Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 DCM Mode
      6. 7.4.6 Light Load Mode
      7. 7.4.7 Foldback Mode
      8. 7.4.8 Forced Pulse-Width-Modulation Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feedforward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitors
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
        14. 8.2.2.14 Synchronization
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Highlights
      2. 10.1.2 Compact Layout for EMI Reduction
      3. 10.1.3 Ground Plane and Thermal Considerations
      4. 10.1.4 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 サポート・リソース
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Pin Functions

PINI/O(1)DESCRIPTION
NO.NAME
1, 2, 3, 4, 5SWPSwitching output of the regulator. Internally connected to the source of the HS FET and drain of the LS FET. Connect to power inductor and bootstrap capacitor.
6BOOTPBootstrap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor from this pin to the SW pin.
7, 19, 23, 27, 28, 29, 30NC—Not internally connected. Connect pins 19, 27, 28, 29, and 30 to ground copper on PCB to improve heat-sinking of the device and board level reliability. Leave pins 7 and 23 floating in order to maximize distance from the high voltage input to ground.
8VCCPOutput of internal bias supply. Used as supply to internal control circuits. Connect a high-quality 2.2-µF capacitor from this pin to GND. TI does not recommended loading this pin by external circuitry.
9BIASPOptional BIAS LDO supply input. TI recommends tying this to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tying to an external 3.3-V or 5-V rail if available, to improve efficiency. When used, place a 1-µF capacitor from this terminal to ground. Tie to ground when not in use.
10RTASwitching frequency setting pin. Place a resistor from this pin to ground to set the switching frequency. If floating, the default switching frequency is 400 kHz. Do not short to ground.
11SS/TRKASoft-start control pin. Leave this pin floating to use the 6.3-ms internal soft-start ramp. An external capacitor can be connected from this pin to ground to extend the soft-start time. A 2-µA current sourced from this pin can charge the capacitor to provide the ramp. Connect to external ramp for tracking. Do not short to ground.
12FBAFeedback input for output voltage regulation. Connect a resistor divider to set the output voltage. Never short this terminal to ground during operation.
16PGOODAOpen-drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = Low when EN = Low
17SYNC/MODEASynchronization input and mode setting pin. Do not float, tie to ground if not used.
Tie to ground: DCM/PFM operation under light loads, improved efficiency
Tie to logic high: forced PWM under light loads, constant switching frequency over load
Tie to external clock source: synchronize switching action to the clock, forced PWM under light loads.
Triggers on the rising edge of external clock.
18ENAPrecision-enable input to regulator. Do not float. High = on, Low = off. Can be tied to VIN. Precision-enable input allows adjustable UVLO by external resistor divider.
13, 14, 15AGNDGAnalog ground. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB.
20, 21, 22PVINPSupply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors CIN. CIN must be placed right next to this pin and PGND and connected with short traces.
24, 25, 26PGNDGPower ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP, AGND, and ground side of CIN and COUT. Path to CIN must be as short as possible.
EPDAP—Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation path for the die. Must be used for heat sinking by soldering to ground copper on PCB. Thermal vias are preferred.
(1) A = Analog, O = Output, I = Input, G = Ground, P = Power