JAJSD27B march   2017  – april 2023 LMG1205

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Start-up and UVLO

The LMG1205 has an undervoltage lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VDD voltage, the UVLO actively pulls the LOL and HOL low. When the VDD voltage is above its UVLO threshold, but the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 7-1 VDD UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below)HILIHOLO
VDD - VSS < VDDR during device start-upHLLL
VDD - VSS < VDDR during device start-upLHLL
VDD - VSS < VDDR during device start-upHHLL
VDD - VSS < VDDR during device start-upLLLL
VDD - VSS < VDDR - VDDH after device start-upHLLL
VDD - VSS < VDDR - VDDH after device start-upLHLL
VDD - VSS < VDDR - VDDH after device start-upHHLL
VDD - VSS < VDDR - VDDH after device start-upLLLL
Table 7-2 VHB-HS UVLO Feature Logic Operation
CONDITION (VDD > VDDR for all cases below)HILIHOLO
VHB-HS < VHBR during device start-upHLLL
VHB-HS < VHBR during device start-upLHLH
VHB-HS < VHBR during device start-upHHLH
VHB-HS < VHBR during device start-upLLLL
VHB-HS < VHBR - VHBH after device start-upHLLL
VHB-HS < VHBR - VHBH after device start-upLHLH
VHB-HS < VHBR - VHBH after device start-upHHLH
VHB-HS < VHBR - VHBH after device start-upLLLL