JAJSQP5B July   2023  – March 2024 LMG2100R044

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Slew Rate Control
        4. 8.2.2.4 Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RAR|16
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

LMG2100R044 RAR Package,17-Pin VQFN(Top View) Figure 4-1 RAR Package,17-Pin VQFN(Top View)
PIN I/O(1) DESCRIPTION
NAME NO.
NC 1–4, 8, 9, 16 — Not connected internally. Leave floating.
SW 5 P Switching node. Internally connected to HS pin.
PGND 6, 17 G Power ground. Low-side GaN FET source. Internally connected to low-side GaN FET source.
VIN 7 P Input voltage pin. Internally connected to high-side GaN FET drain.
HB 10 P High-side gate driver bootstrap rail. Connect bypass capacitor to HS.
HS 11 P High-side GaN FET source connection.
HI 12 I High-side gate driver control input.
LI 13 I Low-side gate driver control input.
VCC 14 P 5V device power supply.
AGND 15 G Analog ground. Internally connected to low-side GaN FET source.
(1) I = Input, O = Output, G = Ground, P = Power