SNOSDH5
November 2024
LMG2640
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Parameter Measurement Information
6.1
GaN Power FET Switching Parameters
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
GaN Power FET Switching Capability
7.3.2
Current-Sense Emulation
7.3.3
Bootstrap Diode Function
7.3.4
Input Control Pins (EN, INL, INH)
7.3.5
INL - INH Interlock
7.3.6
AUX Supply Pin
7.3.6.1
AUX Power-On Reset
7.3.6.2
AUX Under-Voltage Lockout (UVLO)
7.3.7
BST Supply Pin
7.3.7.1
BST Power-On Reset
7.3.7.2
BST Under-Voltage Lockout (UVLO)
7.3.8
Over-Current Protection
7.3.9
Over-Temperature Protection
7.3.10
Fault Reporting
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Solder-Joint Stress Relief
8.4.1.2
Signal-Ground Connection
8.4.1.3
CS Pin Signal
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RRG|40
サーマルパッド・メカニカル・データ
発注情報
snosdh5_oa
snosdh5_pm
Data Sheet
LMG2640
Integrated 650V GaN Half Bridge