JAJSK05D September   2020  – March 2022 LMG3422R030 , LMG3425R030

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Times
      2. 8.1.2 Turn-Off Times
      3. 8.1.3 Drain-Source Turn-On Slew Rate
      4. 8.1.4 Turn-On and Turn-Off Switching Energy
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  GaN FET Operation Definitions
      2. 9.3.2  Direct-Drive GaN Architecture
      3. 9.3.3  Drain-Source Voltage Capability
      4. 9.3.4  Internal Buck-Boost DC-DC Converter
      5. 9.3.5  VDD Bias Supply
      6. 9.3.6  Auxiliary LDO
      7. 9.3.7  Fault Detection
        1. 9.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.7.2 Overtemperature Shutdown
        3. 9.3.7.3 UVLO Protection
        4. 9.3.7.4 Fault Reporting
      8. 9.3.8  Drive Strength Adjustment
      9. 9.3.9  Temperature-Sensing Output
      10. 9.3.10 Ideal-Diode Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Solder-Joint Reliability
      2. 12.1.2 Power-Loop Inductance
      3. 12.1.3 Signal-Ground Connection
      4. 12.1.4 Bypass Capacitors
      5. 12.1.5 Switch-Node Capacitance
      6. 12.1.6 Signal Integrity
      7. 12.1.7 High-Voltage Spacing
      8. 12.1.8 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RQZ|54
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発注情報

7.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
td(on)(Idrain) Drain-current turn-on delay time From VIN > VIN,IT+ to ID > 1 A, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2        28 42 ns
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2        32 52 ns
tr(on) Turn-on rise time From VDS < 320 V to VDS < 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2        2.5 4 ns
td(off) Turn-off delay time  From VIN < VIN,IT– to VDS > 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2        44 65 ns
tf(off) Turn-off fall time(1) From VDS > 80 V to VDS > 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2        21 ns
Minimum IN high pulse-width for FET turn-on VIN rise/fall times < 1 ns, VDS falls to < 200 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1   24 ns
STARTUP TIMES
Driver start-up time From VVDD > VVDD,T+(UVLO) to  FAULT high, CLDO5V = 100 nF, CVNEG = 2.2 µF at 0-V bias linearly decreasing to 1.5 µF at 15-V bias 310 470 us
FAULT TIMES
toff(OC) Overcurrent fault FET turn-off time, FET on before overcurrent VIN = 5 V, From ID > IT(OC) to ID < 50 A, ID di/dt = 100 A/µs 110 145 ns
toff(SC) Short-circuit current fault FET turn-off time, FET on before short circuit VIN = 5 V, From ID > IT(SC) to ID < 50 A, ID di/dt = 700 A/µs 65 100 ns
Overcurrent fault FET turn-off time, FET turning on into overcurrent From ID > IT(OC) to ID < 50 A 200 250 ns
Short-circuit fault FET turn-off time, FET turning on into short circuit From ID > IT(SC) to ID < 50 A 80 180 ns
IN reset time to clear FAULT latch From VIN < VIN,IT– to FAULT high 250 380 580 us
IDEAL-DIODE MODE CONTROL TIMES 
Ideal-diode mode FET turn-on time VDS < VT(3rd) to FET turn-on, VDS being discharged by half-bridge configuration inductor at 5 A 50 65 ns
Ideal-diode mode FET turn-off time ID > IT(ZC) to FET turn-off, ID di/dt = 100 A/µs created with a half-bridge configuration  50 76 ns
Overtemperature-shutdown ideal-diode mode IN falling blanking time  150 230 360 ns
(1) During turn-off, VDS rise time is the result of the resonance of COSS and loop inductance as well as load current.