JAJSK05D September   2020  – March 2022 LMG3422R030 , LMG3425R030

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Times
      2. 8.1.2 Turn-Off Times
      3. 8.1.3 Drain-Source Turn-On Slew Rate
      4. 8.1.4 Turn-On and Turn-Off Switching Energy
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  GaN FET Operation Definitions
      2. 9.3.2  Direct-Drive GaN Architecture
      3. 9.3.3  Drain-Source Voltage Capability
      4. 9.3.4  Internal Buck-Boost DC-DC Converter
      5. 9.3.5  VDD Bias Supply
      6. 9.3.6  Auxiliary LDO
      7. 9.3.7  Fault Detection
        1. 9.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.7.2 Overtemperature Shutdown
        3. 9.3.7.3 UVLO Protection
        4. 9.3.7.4 Fault Reporting
      8. 9.3.8  Drive Strength Adjustment
      9. 9.3.9  Temperature-Sensing Output
      10. 9.3.10 Ideal-Diode Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Solder-Joint Reliability
      2. 12.1.2 Power-Loop Inductance
      3. 12.1.3 Signal-Ground Connection
      4. 12.1.4 Bypass Capacitors
      5. 12.1.5 Switch-Node Capacitance
      6. 12.1.6 Signal Integrity
      7. 12.1.7 High-Voltage Spacing
      8. 12.1.8 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RQZ|54
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER TRANSISTOR
RDS(on) Drain-source on resistance VIN = 5 V, TJ = 25°C 26 35 mΩ
VIN = 5 V, TJ = 125°C 45 mΩ
VSD Third-quadrant mode source-drain voltage IS = 0.1 A 3.8 V
IS = 20 A 3 5 V
IDSS Drain leakage current VDS = 600 V, TJ = 25°C 1 uA
VDS = 600 V, TJ = 125°C 10 uA
COSS Output capacitance VDS = 400 V 130 170 pF
CO(er) Energy related effective output capacitance VDS = 0 V to 400 V 230 276 335 pF
CO(tr) Time related effective output capacitance 430 pF
QOSS Output charge 160 175 nC
QRR Reverse recovery charge 0 nC
VDD – SUPPLY CURRENTS
VDD quiescent current (LMG3422) VVDD = 12 V, VIN = 0 V or 5V 700 1200 uA
VDD quiescent current (LMG3425) VVDD = 12 V, VIN = 0 V or 5V 780 1300 uA
VDD operating current VVDD = 12 V, fIN  = 140 kHz, soft-switching 13 18 mA
BUCK BOOST CONVERTER
VNEG output voltage VNEG sinking 50 mA –14 V
Peak BBSW sourcing current at low peak current mode setting
(Peak external buck-boost inductor current)		 0.3 0.4 0.5 A
Peak BBSW sourcing current at high peak current mode setting
(Peak external buck-boost inductor current)		 0.8 1 1.2 A
High peak current mode setting enable – IN positive-going threshold frequency 280 420 515 kHz
LDO5V
Output voltage LDO5V sourcing 25 mA 4.75 5 5.25 V
Short-circuit current 25 50 100 mA
IN
VIN,IT+ Positive-going input threshold voltage 1.7 1.9 2.45 V
VIN,IT– Negative-going input threshold voltage 0.7 1 1.3 V
Input threshold hysteresis 0.7 0.9 1.3 V
Input pulldown resistance VIN = 2 V 100 150 200 kΩ
FAULT, OC, TEMP – OUPUT DRIVE
Low-level output voltage Output sinking 8 mA 0.16 0.4 V
High-level output voltage Output sourcing 8 mA, Measured as
VLDO5V – VO		 0.2 0.45 V
VDD, VNEG – UNDER VOLTAGE LOCKOUT
VVDD,T+(UVLO) VDD UVLO – positive-going threshold voltage  6.5 7 7.5 V
VDD UVLO – negative-going threshold voltage 6.1 6.5 7 V
VDD UVLO – Input threshold voltage hysteresis 510 mV
VNEG UVLO – negative-going threshold voltage –13.6 –13.0 –12.3 V
VNEG UVLO – positive-going threshold voltage –13.2 –12.75 –12.1 V
GATE DRIVER
Turn-on slew rate From VDS < 320 V to VDS < 80 V, RDRV disconnected from LDO5V, RRDRV = 300 kΩ, TJ = 25℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1   20 V/ns
From VDS < 320 V to VDS < 80 V, TJ = 25℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1    100 V/ns
From VDS < 320 V to VDS < 80 V, RDRV disconnected from LDO5V, VRDRV = 0 V, TJ = 25℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1         150 V/ns
Maximum GaN FET switching frequency. VNEG rising to > –13.25 V, soft-switched, maximum switching frequency derated for VVDD < 9 V  2.2 MHz
FAULTS
IT(OC) DRAIN overcurrent fault – threshold current 60 70 80 A
IT(SC) DRAIN short-circuit fault – threshold current 80 95 110 A
di/dt threshold between overcurrent and short-circuit faults 150 A/µs
Short-circuit current to overcurrent fault trip difference 25 A
GaN temperature fault – postive-going threshold temperature 175 °C
GaN Temperature fault – threshold temperature hysteresis 30 °C
Driver temperature fault – positive-going threshold temperature 185 °C
Driver Temperature fault – threshold temperature hysteresis 20 °C
TEMP
Output Frequency 4.5 9 14 kHz
Output PWM Duty Cycle GaN TJ = 150℃ 82 %
GaN TJ = 125℃ 58.5 64.6 70 %
GaN TJ = 85℃ 36.2 40 43.7 %
GaN TJ = 25℃ 0.3 3 6 %
IDEAL-DIODE MODE CONTROL
VT(3rd) Drain-source third-quadrant detection – threshold voltage –0.15 0 0.15 V
IT(ZC) Drain zero-current detection – threshold current 0℃ ≤ TJ ≤ 125℃ –0.2 0 0.2 A
–40℃ ≤ TJ ≤ 0℃ –0.35 0 0.35 A