JAJSR52 September   2023 LMG3526R050

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-On Times
      2. 7.1.2 Turn-Off Times
      3. 7.1.3 Drain-Source Turn-On Slew Rate
      4. 7.1.4 Zero-Voltage Detection Times
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN FET Operation Definitions
      2. 8.3.2  Direct-Drive GaN Architecture
      3. 8.3.3  Drain-Source Voltage Capability
      4. 8.3.4  Internal Buck-Boost DC-DC Converter
      5. 8.3.5  VDD Bias Supply
      6. 8.3.6  Auxiliary LDO
      7. 8.3.7  Fault Detection
        1. 8.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 8.3.7.2 Overtemperature Shutdown
        3. 8.3.7.3 UVLO Protection
        4. 8.3.7.4 Fault Reporting
      8. 8.3.8  Drive-Strength Adjustment
      9. 8.3.9  Temperature-Sensing Output
      10. 8.3.10 Ideal-Diode Mode Operation
        1. 8.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
      11. 8.3.11 Zero-Voltage Detection (ZVD)
    4. 8.4 Start-Up Sequence
    5. 8.5 Safe Operation Area (SOA)
      1. 8.5.1 Repetitive SOA
    6. 8.6 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Using an Isolated Power Supply
      2. 9.4.2 Using a Bootstrap Diode
        1. 9.4.2.1 Diode Selection
        2. 9.4.2.2 Managing the Bootstrap Voltage
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Solder-Joint Reliability
        2. 9.5.1.2 Power-Loop Inductance
        3. 9.5.1.3 Signal-Ground Connection
        4. 9.5.1.4 Bypass Capacitors
        5. 9.5.1.5 Switch-Node Capacitance
        6. 9.5.1.6 Signal Integrity
        7. 9.5.1.7 High-Voltage Spacing
        8. 9.5.1.8 Thermal Recommendations
      2. 9.5.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 Export Control Notice
    7. 10.7 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 GaN FET Operation Definitions

For the purposes of this data sheet, the following terms are defined below. The SOURCE pin is assumed to be at 0 V for these definitions.

First-Quadrant Current = Positive current flowing internally from the DRAIN pin to the SOURCE pin.

Third-Quadrant Current = Positive current flowing internally from the SOURCE pin to the DRAIN pin.

First-Quadrant Voltage = Drain pin voltage – Source pin voltage = Drain pin voltage

Third-Quadrant Voltage = SOURCE pin voltage – DRAIN pin voltage = –DRAIN pin voltage

FET On-State = FET channel is at rated RDS(on). Both first-quadrant current and third-quadrant current can flow at rated RDS(on).

For LMG3526R050 in On-State, GaN FET internal gate voltage is held at the SOURCE pin voltage to achieve rated RDS(on). The GaN FET channel is at rated RDS(on) with VGS = 0 V because the LMG3526R050 GaN FET is a depletion mode FET.

FET Off-State = FET channel is fully off for positive first-quadrant voltage. No first-quadrant current can flow. While first-quadrant current cannot flow in the FET Off-State, third-quadrant current still flows if the DRAIN voltage is taken sufficiently negative (positive third-quadrant voltage). For devices with an intrinsic p-n junction body diode, current flow begins when the DRAIN voltage drops enough to forward bias the p-n junction.

GaN FETS do not have an intrinsic p-n junction body diode. Instead, current flows because the GaN FET channel turns back on. In this case, the DRAIN pin becomes the electrical source and the SOURCE pin becomes the electrical drain. To enhance the channel in third-quadrant, the DRAIN (electrical source) voltage must be taken sufficiently low to establish a VGS voltage greater than the GaN FET threshold voltage. The GaN FET channel is operating in saturation and only turns on enough to support the third-quadrant current as its saturated current.

For LMG3526R050 in Off-State, GaN FET internal gate voltage is held at the VNEG pin voltage to block all first-quadrant current. The VNEG voltage is lower than the GaN FET negative threshold voltage to cut off the channel.

To enhance the channel in off-state third quadrant, the LMG3526R050 DRAIN (electrical source) voltage must be taken sufficiently close to VNEG to establish a VGS voltage greater than the GaN FET threshold voltage. Again, because the LMG3526R050 GaN FET is a depletion mode FET with a negative threshold voltage, this means the GaN FET turns on with DRAIN (electrical source) voltage between 0 V and VNEG. The typical off-state third-quadrant voltage is 5.3 V for third-quadrant current at 15 A. Thus, the off-state third-quadrant losses for the LMG3526R050 are significantly higher than a comparable power device with an intrinsic p-n junction body diode.