JAJSR52 September   2023 LMG3526R050

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-On Times
      2. 7.1.2 Turn-Off Times
      3. 7.1.3 Drain-Source Turn-On Slew Rate
      4. 7.1.4 Zero-Voltage Detection Times
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN FET Operation Definitions
      2. 8.3.2  Direct-Drive GaN Architecture
      3. 8.3.3  Drain-Source Voltage Capability
      4. 8.3.4  Internal Buck-Boost DC-DC Converter
      5. 8.3.5  VDD Bias Supply
      6. 8.3.6  Auxiliary LDO
      7. 8.3.7  Fault Detection
        1. 8.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 8.3.7.2 Overtemperature Shutdown
        3. 8.3.7.3 UVLO Protection
        4. 8.3.7.4 Fault Reporting
      8. 8.3.8  Drive-Strength Adjustment
      9. 8.3.9  Temperature-Sensing Output
      10. 8.3.10 Ideal-Diode Mode Operation
        1. 8.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
      11. 8.3.11 Zero-Voltage Detection (ZVD)
    4. 8.4 Start-Up Sequence
    5. 8.5 Safe Operation Area (SOA)
      1. 8.5.1 Repetitive SOA
    6. 8.6 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Using an Isolated Power Supply
      2. 9.4.2 Using a Bootstrap Diode
        1. 9.4.2.1 Diode Selection
        2. 9.4.2.2 Managing the Bootstrap Voltage
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Solder-Joint Reliability
        2. 9.5.1.2 Power-Loop Inductance
        3. 9.5.1.3 Signal-Ground Connection
        4. 9.5.1.4 Bypass Capacitors
        5. 9.5.1.5 Switch-Node Capacitance
        6. 9.5.1.6 Signal Integrity
        7. 9.5.1.7 High-Voltage Spacing
        8. 9.5.1.8 Thermal Recommendations
      2. 9.5.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 Export Control Notice
    7. 10.7 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE connected with reference ground; –40℃ ≤ TJ ≤ 125℃; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V;  LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
td(on)(Idrain) Drain-current turn-on delay time From VIN > VIN,IT+ to ID > 1 A, VBUS = 400 V, LHB current = 10 A, see Figure 7-1 and Figure 7-2        28 40 ns
td(on) Turn-on delay time  From VIN > VIN,IT+ to VDS < 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 7-1 and Figure 7-2    37 45 ns
tr(on) Turn-on rise time From VDS < 320 V to VDS < 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 7-1 and Figure 7-2        2.5 4 ns
td(off) Turn-off delay time  From VIN < VIN,IT– to VDS > 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 7-1 and Figure 7-2      44 60 ns
tf(off) Turn-off fall time(1) From VDS > 80 V to VDS > 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 7-1 and Figure 7-2        15 ns
Minimum IN high pulse-width for FET turn-on VIN rise/fall times < 1 ns, VDS falls to < 200 V, VBUS = 400 V, LHB current = 10 A, see Figure 7-1   24 ns
STARTUP TIMES
t(start) Driver start-up time From VVDD > VVDD,T+(UVLO) to FAULT high, CLDO5V = 100 nF, CVNEG = 2.2 µF at 0-V bias linearly decreasing to 1.5 µF at 15-V bias 470 µs
FAULT TIMES
toff(OC) Overcurrent fault FET turn-off time, FET on before overcurrent VIN = 5 V, From ID > IT(OC) to ID < 50 A, ID di/dt = 100 A/µs 110 170 ns
toff(SC) Short-circuit current fault FET turn-off time, FET on before short circuit VIN = 5 V, From ID > IT(SC) to ID < 50 A, ID di/dt = 700 A/µs 55 100 ns
Overcurrent fault FET turn-off time, FET turning on into overcurrent From ID > IT(OC) to ID < 50 A 200 250 ns
Short-circuit fault FET turn-off time, FET turning on into short circuit From ID > IT(SC) to ID < 50 A 115 180 ns
IN reset time to clear FAULT latch From VIN < VIN,IT– to FAULT high 250 380 580 µs
t(window)(OC) Overcurrent fault to short-circuit fault window time 50 ns
IDEAL-DIODE MODE CONTROL TIMES
Ideal-diode mode FET turn-on time VDS < VT(3rd) to FET turn-on, VDS being discharged by half-bridge configuration inductor at 5 A 50 75 ns
Ideal-diode mode FET turn-off time ID > IT(ZC) to FET turn-off, ID di/dt = 100 A/µs created with a half-bridge configuration 55 76 ns
Overtemperature-shutdown ideal-diode mode IN falling blanking time  150 230 360 ns
ZERO VOLTAGE DETECTION TIMES
tWD_ZVD ZVD Pulse Width See Figure 7-3 75 100 140 ns
tDL_ZVD Time delay between IN rise to ZVD pulse's rising edge See Figure 7-3 15 30 ns
t3rd_ZVD 3rd quadrant conduction time when the ZVD pulse starts to appear Vbus = 10 V, IL = 5 A, Rdrv = 5 V, measure the 3rd quadrant conduction time when the ZVD pulse starts to appear. See Figure 7-3 42 56 ns
(1) During turn off, VDS rise time is the result of the resonance of COSS and loop inductance, as well as load current.