JAJSRA4 September   2023 LMG3624

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GaN Power FET Switching Capability
      2. 8.3.2 Turn-On Slew-Rate Control
      3. 8.3.3 Current-Sense Emulation
      4. 8.3.4 Input Control Pins (EN, IN)
      5. 8.3.5 AUX Supply Pin
        1. 8.3.5.1 AUX Power-On Reset
        2. 8.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Overtemperature Protection
      8. 8.3.8 Fault Reporting
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

1) Symbol definitions: ID = D to S current;  IS = S to D current; ICS(src) = current out of CS;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; 10 V ≤ VAUX ≤ 26 V; VEN = 5 V; VIN = 0 V; RRDRV = 0 Ω; RCS = 100 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET 
RDS(on) Drain-source (D to S) on resistance  VIN = 5 V, ID = 3 A, TJ = 25°C 170 mΩ
VIN = 5 V, ID = 3 A, TJ = 125°C 335
VSD Source-drain (S to D) third-quadrant voltage IS = 0.3 A –2.1 V
IS = 3 A –2.9
IDSS Drain (D to S) leakage current VDS = 650 V, TJ = 25°C 2 µA
VDS = 650 V, TJ = 125°C 10
QOSS Output (D to S) charge VDS = 400 V 19.7 nC
COSS Output (D to S) capacitance 22 pF
EOSS Output (D to S) capacitance stored energy 2.32 µJ
COSS,er Energy related effective output (D to S) capacitance 29 pF
COSS,tr Time related effective output (D to S) capacitance VDS = 0 V to 400 V 49.2 pF
QRR Reverse recovery charge 0 nC
OVERCURRENT PROTECTION
IT(OC) Overcurrent fault - threshold current 5.4 6 6.6 A
CS
Current sense gain (ICS(src) / ID) VIN = 5 V, 0 V ≤ VCS ≤ 2 V, 0 A ≤ ID < IT(OC) 0.916 0.965 1.014 mA/A
Current sense input offset current VIN = 5 V, 0 V ≤ VCS ≤ 2 V, 0 A ≤ ID < IT(OC) –55 55 mA
Initial held output after overcurrent fault occurs while IN remains high VIN = 5 V, 0 V ≤ VCS ≤ 2 V 7 mA
ICS(src)(OC)(final) Final held output after overcurrent fault occurs while IN remains high VIN = 5 V, 0 V ≤ VCS ≤ 2 V 10 12 15.5 mA
Output clamp voltage VIN = 5 V, ID = 5.2 A, CS sinking 5 mA from external source 2.5 V
EN, IN
VIT+ Positive-going input threshold voltage 1.7 2.45 V
VIT– Negative-going input threshold voltage 0.7 1.3 V
Input threshold voltage hysteresis 1 V
Pull-down input resistance 0 V ≤ VPIN ≤ 3 V 200 400 600 kΩ
Pull-down input current 10 V ≤ VPIN ≤ 26 V; VAUX = 26 V 10 µA
OVERTEMPERATURE PROTECTION
Temperature fault – postive-going threshold temperature 165 °C
Temperature fault – negative-going threshold temperature 145 °C
Temperature fault – threshold temperature hysteresis 20 °C
FLT
Low-level output voltage FLT sinking 1 mA while asserted 200 mV
Off-state sink current VFLT = VAUX while de-asserted 1 µA
AUX
VAUX,T+(UVLO) UVLO – positive-going threshold voltage 8.9 9.3 9.7 V
UVLO – negative-going threshold voltage 8.6 9.0 9.4 V
UVLO – threshold voltage hysteresis 250 mV
Standby quiescent current VEN = 0 V 50 80 µA
Quiescent current 240 360 µA