JAJSRA4A September   2023  – June 2024 LMG3624

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Current-Sense Emulation
      4. 7.3.4 Input Control Pins (EN, IN)
      5. 7.3.5 AUX Supply Pin
        1. 7.3.5.1 AUX Power-On Reset
        2. 7.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 7.3.6 Overcurrent Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
        2. 8.2.2.2 Current-Sense Design
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Switching Characteristics

1) Symbol definitions: ID = D to S current;  IS = S to D current; ICS(src) = current out of CS;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; VDS = 520V; 10V ≤ VAUX ≤ 26V; VEN = 5V; VIN = 0V; RRDRV = 0Ω; RCS = 100Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET 
td(on)(Idrain) Drain current turn-on delay time From VIN > VIN,IT+ to ID > 37.5mA, VBUS = 400V, LHB current = 1.5A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 64 ns
slew rate setting 1 31
slew rate setting 2 26
slew rate setting 3 (fastest) 23
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 1.5A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 86 ns
slew rate setting 1 40
slew rate setting 2 34
slew rate setting 3 (fastest) 27
td(off) Turn-off delay time From VIN < VIN,IT– to VDS > 80V, VBUS = 400V, LHB current = 1.5A, (independent of slew rate setting), see GaN Power FET Switching Parameters 32 ns
tf(off) Turn-off fall time From VDS > 80V to VDS > 320V, VBUS = 400V, LHB current = 1.5A, (independent of slew rate setting), see GaN Power FET Switching Parameters 22 ns
Turn-on slew rate From VDS < 250V to VDS < 150V, TJ = 25℃, VBUS = 400V, LHB current = 1.5A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 20 V/ns
slew rate setting 1 50
slew rate setting 2 75
slew rate setting 3 (fastest) 150
CS
tr Rise time From ICS(src) > 0.2 × ICS(src)(final) to ICS(src) > 0.9 × ICS(src)(final), 0V ≤ VCS ≤ 2V, enabled into a 1.5A load 35 ns
EN
EN Wake-up time From VEN > VIT+ to ID(ls) > 10mA, VINL = 5V 1.5 µs