JAJSRA3A September   2023  – November 2023 LMG3626

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Current-Sense Emulation
      4. 7.3.4 Input Control Pins (EN, IN)
      5. 7.3.5 AUX Supply Pin
        1. 7.3.5.1 AUX Power-On Reset
        2. 7.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 7.3.6 Overcurrent Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Fault Reporting
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
        2. 8.2.2.2 Current-Sense Design
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Current-Sense Emulation

The current-sense emulation function creates a scaled replica of the GaN power FET positive drain current at the output of the CS pin. The current-sense emulation gain, GCSE, is 1.633-mA output from the CS pin, ICS, for every 1 A passing into the drain of the low-side GaN power FET, ID.

Equation 1. GCSE = ICS / ID = 1.633 mA / 1 A = 0.001633

The CS pin is terminated with a resistor to AGND, RCS, to create the current-sense voltage input signal to the external power supply controller.

RCS is determined by solving for the traditional current-sense design resistance, RCS(trad), and multiplying by the inverse of GCSE. The traditional current-sense design creates the current-sense voltage, VCS(trad), by passing the GaN power FET drain current, ID, through RCS(trad). The LMG3626 creates the current-sense voltage, VCS, by passing the CS pin output current, ICS, through RCS. The current-sense voltage must be the same for both designs.

Equation 2. VCS = ICS × RCS = VCS(trad) = ID × RCS(trad)
Equation 3. RCS = ID / ICS × RCS(trad) = 1 / GCSE × RCS(trad)
Equation 4. RCS = 612 × RCS(trad)

The CS pin is clamped internally to a typical 2.5 V. The clamp protects vulnerable power-supply controller current-sense input pins from over voltage if, for example, the current sense resistor on the CS pin were to become disconnected.

Figure 7-2 shows the current-sense emulation operation. In both cycles, the CS pin current emulates the GaN power FET drain current while the GaN FET is enabled. The first cycle shows normal operation where the controller turns off the GaN power FET when the controller current-sense input threshold is tripped. The second cycle shows a fault situation where the LMG3626 overcurrent protection turns off the GaN power FET before the controller current-sense input threshold is tripped. In this second cycle, the LMG2610 avoids a hung controller IN pulse by generating a fast-ramping artificial current-sense emulation signal to trip the controller current-sense input threshold. The artificial signal persists until the IN pin goes to logic-low which indicates the controller is back in control of switch operation.


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Figure 7-2 Current-Sense Emulation Operation