SNOSDL1 December 2024 LMG3650R035
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SWITCHING TIMES | ||||||
td(on) | Turn-on delay time | From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 0A, 100V/ns | 30 | 45 | ns | |
tir(on) | Turn-on current rise time + delay time | From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 10A, 100V/ns | 35 | 60 | ns | |
tvf(on) | Turn-on voltage falling time | From VDS < 320V to VDS < 80V, VBUS = 400V, LHB current = 10A, 100V/ns | 1 | 2.3 | 3 | ns |
tvf_peak(on) | Turn-on slew rate | dv/dt when VDS = 200V, VBUS = 400V, LHB current = 10A, 100V/ns | 90 | 115 | 150 | V/ns |
Pulse width distortion | slew-rate setting at 100V/ns | 20 | ns | |||
Minimum input pulse changing the output L-H-L | slew-rate setting at 100V/ns such that SW crosses 200V | 50 | ns | |||
td(off) | Turn-off delay time at full speed | From VIN < 2.5V to VDS >= 10V. VBUS = 400V, IL = 34A, fastest or full turn-off speed. | 12 | 17 | 35 | ns |
tvr(off) | Turn-off voltage rise time at full speed | From VDS >= 20V to VDS >= 380V. VBUS = 400V, IL = 34A, fastest or full turn-off speed. | 3 | 4.5 | 7 | ns |
STARTUP TIMES | ||||||
TDRV_START | Driver startup delay | From Driver supply crossing UVLO to switch turning on if IN is high. | 35 | 65 | µs | |
FAULT TIMES | ||||||
toff(OC) | Overcurrent fault FET turn-off time, FET on before overcurrent | From ID >= IT(OC) to Vds> 10V, di/dt = 100A/µs, in the fastest turn-off speed | 370 | 480 | ns | |
toff(OC_ON) | Overcurrent total on time, turn-on into overcurrent. | From Vds <= 10V to Vds >= 10V, turning on at 110% of OC level, at 100 V/ns turn-on slew rate and fastest turn-off speed. | 420 | 580 | ns | |
toff_cur(SC_ON) | SC on time measured through drain current | From LS Ids > 50A to Ids < 50A, at 100 V/ns turn-on slew rate in a half-bridge configuration. | 100 | 500 | ns | |
toff_cur(SC) | SC response time with source current measurement | From LS Vds>9V to LS Ids<50A, at 100 V/ns turn-on slew rate in a half-bridge configuration. . | 300 | ns | ||
Latched-Fault reset time | Time required to hold both gate driver input low to clear latched-fault | 300 | 380 | 450 | µs | |
ZCD/ZVD | ||||||
ZCD delay | Current crossing zero (low to high) to ZCD output pulse di/dt = 0.03A/ns | 12 | 25 | 40 | ns | |
ZVD delay | In rising to ZVD output pulse. 100V/ns turn-on speed. | 13 | 20 | 50 | ns | |
tWD_ZVD | ZVD pulse width | Vbus = 10V, IL = 5A, measure ZVD pulse width | 90 | 120 | 170 | ns |
ZVD sensing time | Sensing time to fet turn on (100V/ns). IL=2A | 11 | 25 | ns |