The CFG1-pin defines the Clock Dithering, the 120% input current limit protection (I_{CL_latch}) and max. Overvoltage Protection behavior (OVP_{max_latch}), the sense voltage and the gate driver strength. The levels shown in Table 6-1 are selected by the specified resistors in Section 5.

Device Clock Dithering, I_{CL_latch} & OVP_{max_latch}, Sense Voltage and Gate Drive Strength

• Spread Spectrum: Enables dual random spread spectrum (DRSS) clock dithering or disables clock dithering.
• I_{CL_latch}& OVP_{max_latch}: When I_{CL_latch} is enabled and the peak current limit is exceeded by 20% the device goes to the Shutdown State (turns off and is latched). If I_{CL_latch} is disabled the device stays active and tries to limit the inductor current at peak current limit. When OVP_{max_latch} is enabled and V_OUT reached the max. set OVP level the device goes to the Shutdown state (turns off and is latched).
• Sense Voltage: The device peak current voltage V_{CSA - CSB)} at the sense resistor can be set to 30mV or 60mV.
• Gate Drive Strength: The internal GaN FET gate driver strength can be set to weak (slower switch node rising/falling) or strong (faster switch node rising/falling). For highest performance (efficiency), the strong setting can be used, while for lowest EMI or not optimized PCB layout the weak setting is the better choice.
• SYNCIN: Defines if the clock syncing function at the SYNCIN-pin is active (on) or disabled (off). The device is only syncing to an external clock applied to the SYNCIN-pin when SYNCIN is active.
• Clock Dithering: In case the internal oscillator is used the clock dithering is set according to the CFG1-pin setting Clock Dithering Mode. When an external clock is used the clock dithering function is disabled ignoring the CFG1-pin setting.

The CFG2-pin defines both the power good pin OVP behavior and if the device uses the internal clock generator or an external clock applied at the SYNCIN-pin. Additionally, the CFG2-pin configures if the device is used as a single device or part of a multi device configuration, the SYNCIN and SYNCOUT-pin is enabled/disabled accordingly. During clock synchronization the clock dither function is disabled. The levels shown in Table 6-2 are selected by the specified resistors in Section 5.

PGOOD_{OVP_enable}, Single / Multichip, SYNCIN, SYNCOUT and Clock Dithering

• PGOOD_{OVP_enable}: When PGOOD_{OVP_enable} is enabled the PGOOD-pin is pulled low for V_OUT above OVP (Over Voltage Protection) or below the UV (Under Voltage) threshold. If PGOOD_{OVP_enable} is disabled the PGOOD-pin is only pulled low when V_OUT is below UV (Under Voltage) threshold.
• Singleor Multichip: Defines if the device is used stand-alone (single) using the internal oscillator or an external clock. When SYNCIN is on the clock signal applied at SYNCIN is used. In case no clock is applied or the clock is stopped the device switches to the internal oscillator.
• Primary: Device is used as primary device acting as a controller in a multi device configuration using the internal oscillator when no clock is applied at SYNCIN-pin. At the SYNCOUT-pin a phase shifted clock (90°, 120° or 180°) is generated for the next device.
• Secondary: Device is used as secondary device syncing the clock to the SYNCIN-pin signal. At the SYNCOUT-pin a phase shifted clock (90° or 120°) can be generated for the next device.

The SYNCOUT-pin is used at startup to define the VOUT Over Voltage Protection level (OVPmax) and the 20μA. ATRK-pin current. When VOUT is programmed by resistor the 20μA ATRK-pin current must be on, for voltage tracking current must be off. The levels shown in Table 6-3 are selected by the specified resistors in Section 5.

OVP, Spread Spectrum, Peak Current Limit Latch, Power Good Pin Behavior

• OVP_max: Sets the V_OUT max. overvoltage protection level to 25V, 35V, 50V or 65V.
• 20μA ATRK-pin current: Enables and disables the 20μA ATRK-pin current.