JAJSVT7 December   2024 LMG5126

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Configuration
      2. 6.3.2 Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3 Dual Random Spread Spectrum (DRSS)
      4. 6.3.4 Operation Modes (BYPASS, DEM, FPWM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Determining the Duty Cycle
        2. 7.2.3.2 Timing Resistor RT
        3. 7.2.3.3 Vout Programming
        4. 7.2.3.4 Inductor Selection Lm
        5. 7.2.3.5 Output Capacitor Cout
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • VBT|22
サーマルパッド・メカニカル・データ

5 Specifications

Product Preview Samples

Note:

The current devices marked XSE5126 have the following limitations. The next silicon sampling early Q2 2025 resolves the limitations:

Diode Emulation Mode (DEM) does not work at light load.

  • Boot refreshing does not function as intended in DEM operation. Boot undervoltage event initiates low-side FET switching, but boot switch blocks boot capacitor charging. Repeated boot undervoltage trigger may cause VOUT runaway. Boot refreshing does not operate in DEM therfore device cannot turn on the high-side switch at light load.
  • DEM can only be used (activated) for loads high enough so boot refresh is not needed (usually for IOUT >50mA).
  • It is recommended to keep the device in FPWM operation mode (MODE-pin = high).

High-side FET is not turning on for low inductor peak currents

  • For inductor peak currents between 1A and about 5A (VOUT dependant) the high side FET does not turn on causing higher losses.
  • It is recommended to connect the BIAS-pin to 5V. This narrows down the peak current range where the high-side FET does not turn on.
  • For efficiency measurements, it is recommended to connect the BIAS-pin to ≥5V (e.g.VI ).
    • For VI = 12V and VOUT = 24V a load >1A is recommended to get valid efficiency measurements.
    • For VI = 12V and VOUT = 48V a load >0.5A is recommended to get valid efficiency measurements.

Automatic BIAS supply switchover BIAS-pin to VOUT-pin is disabled.

  • As a result BIAS-pin voltage must be >4.5V.

Do not trigger thermal shutdown. Limit device temperature to 150°C max.

  • The device can get damaged when thermal shutdown is triggered and a constant current load is applied. The device stops switching at thermal shutdown causing VOUT to collapse to VI. The around 2.5V reverse conduction threshold of the high-side FET then generates significant losses as the load is still applied. The high-side FET rapidly heats up and can get damaged.
  • It is recommended to evaluate the device with assembled top-side heat sink only.

Do not trigger ICL latch feature as the device behaves as described for thermal shutdown.

When VI is close to VOUT (e.g. Bypass-Mode) a timing violation inside the device can happen.

  • When the device operates at min tON a timing violation can cause the low-side FET to turn on but not off for one cycle. This results in cross conduction for one cycle.
  • It is recommended to avoid min tON operation. The min. tON time should be >150ns.