JAJSVT7 December   2024 LMG5126

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Configuration
      2. 6.3.2 Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3 Dual Random Spread Spectrum (DRSS)
      4. 6.3.4 Operation Modes (BYPASS, DEM, FPWM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Determining the Duty Cycle
        2. 7.2.3.2 Timing Resistor RT
        3. 7.2.3.3 Vout Programming
        4. 7.2.3.4 Inductor Selection Lm
        5. 7.2.3.5 Output Capacitor Cout
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • VBT|22
サーマルパッド・メカニカル・データ

7.4.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. Poor PCB design can cause among others converter instability, load regulation problems, noise or EMI issues. Thermal relieved connections in the power path for VCC should not be used as they add significant inductance.

  • Place the VCC and BIAS capacitors close to the corresponding device pins and connect them with short and wide traces to minimize inductance as they carry high peak currents.
  • Place CSA and CSB filter resistors and capacitors close to the corresponding device pins to minimize noise coupling between the filter and the device. Route the traces to the sense resistor RCS, which is placed close to the inductor, as differentail pair and surrounded by ground to avoide noise coupling. Use Kelvin connections to the sense resistor.
  • Place the compensation network RCOMP and CCOMP as well as the frequency setting resistor RRT close to the corresponding device pins and connect them with short traces to avoide noise coupling. Connect the analog ground pin AGND to these components.
  • Place the ATRK resistor RATRK (when used) close to the ATRK pin and connect it to AGND.
  • The layout of following components is not so critical:
    • Soft-Start capacitor CSS
    • DLY capacitor CDLY
    • ILIM/IMON resitor and capacitor RILIM and CILIM
    • CFG1, CFG2 and SYNCOUT resistors
    • UVLO/EN resistors
  • Place the filter VOUT capacitors (small size ceramic) close to the VOUT-pin. Use short and wide traces to minimize the power stage loop COUT to VOUT connection to avoid high voltage spikes.
  • Connect the PGND-pin connection with short and wide traces to the VOUT and VI capacitors ground to minimize inductance causing high voltage spikes.
  • It is recommended to connect the AGND and PGND pin directly to the exposed pad (EP) to form a star connection at the device.
  • Connect the device exposed pad (EP) with several vias to a ground plane to conduct heat away.
  • Seperate power and signal traces and use a ground plane to provide noise shielding.

To spread the heat generated by the converter and the inductor, the inductor should be placed away from the converter. However the longer the trace between the inductor and the converter the higher the EMI and noise emissions. For highest efficiency the inductor should be connected by wide and short traces to minimize resistive losses.