JAJSVT7 December   2024 LMG5126

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Configuration
      2. 6.3.2 Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3 Dual Random Spread Spectrum (DRSS)
      4. 6.3.4 Operation Modes (BYPASS, DEM, FPWM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Determining the Duty Cycle
        2. 7.2.3.2 Timing Resistor RT
        3. 7.2.3.3 Vout Programming
        4. 7.2.3.4 Inductor Selection Lm
        5. 7.2.3.5 Output Capacitor Cout
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • VBT|22
サーマルパッド・メカニカル・データ

6.1 Overview

The LMG5126 is a wide input range boost converter using integrated GaN FETs. The device provides a regulated output voltage if the input voltage is equal or lower than the adjusted output voltage. The resistor-to-digital (R2D) interface offers the user a simple and robust selection of all the device functionality.

The operation modes DEM (Diode Emulation Mode) and FPWM (Forced Pulse Width Modulation) are on-the-fly pin-selectable during operation. The peak current mode control operates with fixed switching frequency set by the RT-pin. Through the activation of the dual random spread spectrum operation, EMI mitigation is achievable at any time of the design process.

The integrated average current monitor can help monitor or limit input current. The output voltage can be dynamically adjusted during operation (dynamic voltage scaling and envelope tracking). The adjustment is either possible by changing the analog reference voltage of the ATRK/DTRK-pin or the adjustment can be done directly with a PWM input signal on the ATRK/DTRK-pin.

The internal wide input LDOs provide a robust supply of the device functionality under different input and output voltage conditions. Due to the high drive capability and the automatic and headroom depended voltages selection, the power losses are kept at a minimum. The separate BIAS-pin can be connected to the input, output, or an external supply to further reduce power losses in the device. At all times, the internal supply voltage is monitored to avoid undefined failure handling.

The devices built-in protection features provide a safe operation under different fault conditions. There is a VI undervoltage lockout protection to avoid brownout situations. Because the input UVLO threshold and hysteresis can be configured through an external feedback divider, the brownout is avoided under the different designs. The device has an output overvoltage protection. The selectable hiccup overcurrent protection avoids excessive short circuit currents by using the internal cycle-by-cycle peak current protection. Due to the integrated thermal shutdown, the device is protected against thermal damage caused by an overload condition. All output-related fault events are monitored and indicated at the open-drain PGOOD-pin of the device.