JAJSFL5D April   2016  – June 2018 LMH1219

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface AC Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Input Configuration Pins
      2. 8.3.2  Input Carrier Detect
      3. 8.3.3  -6 dB Splitter Mode Launch Amplitude for IN0
      4. 8.3.4  Continuous Time Linear Equalizer (CTLE)
        1. 8.3.4.1 Adaptive Cable Equalizer (IN0+)
        2. 8.3.4.2 Adaptive PCB Trace Equalizer (IN1±)
      5. 8.3.5  Input-Output Mux Selection
      6. 8.3.6  Clock and Data Recovery (CDR) Reclocker
      7. 8.3.7  Internal Eye Opening Monitor (EOM)
      8. 8.3.8  Output Function Control
      9. 8.3.9  Output Driver Amplitude and De-Emphasis Control
      10. 8.3.10 Status Indicators and Interrupts
        1. 8.3.10.1 LOCK_N (Lock Indicator)
        2. 8.3.10.2 CD_N (Carrier Detect)
        3. 8.3.10.3 INT_N (Interrupt)
      11. 8.3.11 Additional Programmability
        1. 8.3.11.1 Cable Length Indicator (CLI)
        2. 8.3.11.2 Digital MUTEREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Management Bus (SMBus) Mode
        1. 8.4.1.1 SMBus Read and Write Transactions
          1. 8.4.1.1.1 SMBus Write Operation Format
          2. 8.4.1.1.2 SMBus Read Operation Format
      2. 8.4.2 Serial Peripheral Interface (SPI) Mode
        1. 8.4.2.1 SPI Read and Write Transactions
          1. 8.4.2.1.1 SPI Write Transaction Format
          2. 8.4.2.1.2 SPI Read Transaction Format
        2. 8.4.2.2 SPI Daisy Chain
    5. 8.5 LMH1219 Register Map
      1. 8.5.1 Share Register Page
      2. 8.5.2 CTLE/CDR Register Page
      3. 8.5.3 CableEQ/Drivers Register Page
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Guidance for SMPTE and 10 GbE Applications
      2. 9.1.2 Optimizing Time to Adapt and Lock
      3. 9.1.3 LMH1219 and LMH0324 Compatibility
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detail Design Procedure
      3. 9.2.3 Recommended VOD and DEM Register Settings
      4. 9.2.4 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 PCB Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.2 Optimizing Time to Adapt and Lock

When carrier detect is asserted the LMH1219 continuously adapts the cable equalizer to the optimal gain and bandwidth. The time required to adapt the equalizer and achieve lock to the incoming signal can be optimized by manually programming the highest data rate expected in the application. Refer to LMH1219 programming guide for more details.