JAJSFL6D April   2016  – June 2018 LMH1226

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Pins
      2. 7.3.2 Input Carrier Detect
      3. 7.3.3 Continuous Time Linear Equalizer (CTLE)
        1. 7.3.3.1 Adaptive PCB Trace Equalizer (IN1±)
      4. 7.3.4 Input-Output Mux Selection
      5. 7.3.5 Clock and Data Recovery (CDR) Reclocker
      6. 7.3.6 Internal Eye Opening Monitor (EOM)
      7. 7.3.7 Output Function Control
      8. 7.3.8 Output Driver Amplitude and De-Emphasis Control
      9. 7.3.9 Status Indicators and Interrupts
        1. 7.3.9.1 LOCK_N (Lock Indicator)
        2. 7.3.9.2 CD_N (Carrier Detect)
        3. 7.3.9.3 INT_N (Interrupt)
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH1226 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CTLE/CDR Register Page
      3. 7.5.3 Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE and 10 GbE Applications
      2. 8.1.2 LMH1219 and LMH1226 Compatibility
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Recommended VOD and DEM Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PDDUAL Power Dissipation, Dual Supply Mode Measured with PRBS-10, Locked to 11.88 Gbps, only OUT1 enabled 214 mW
PDZ_DUAL Power Dissipation, Dual Supply Mode Power Save Mode, no input signal 16 mW
PDSINGLE Power Dissipation, Single Supply Mode Measured with PRBS-10, Locked to 11.88 Gbps, only OUT1 enabled 227 mW
PDZ_SINGLE Power Dissipation, Single Supply Mode Power Save Mode, no input signal 27 mW
IDDDUAL Current Consumption, Dual Supply Mode Measured at 2.5 V supply with PRBS-10, Locked to 11.88 Gbps, VOD = Default, only OUT1 enabled 73 80 mA
Measured at 1.8 V supply with PRBS-10, Locked to 11.88 Gbps, VOD = Default, only OUT1 enabled 17 25
IDDZ_DUAL Current Consumption, Dual Supply Mode Forced Power Save Mode, MODE_SEL = LEVEL-H, measured at 2.5 V supply 4 5 mA
Forced Power Save Mode, MODE_SEL = LEVEL-H, measured at 1.8 V supply 3 9
IDDTRANS_DUAL Current Consumption, Dual Supply Mode, Acquiring Lock, HEO/VEO Lock Monitor Disabled Measured at 2.5 V supply with PRBS-10, Acquiring Lock, VOD = Default, OUT0 and OUT1 enabled 90 101 mA
Measured at 1.8 V supply with PRBS-10, Acquiring Lock, VOD = Default, OUT0 and OUT1 enabled 30 37
VDDLDO LDO 1.8 V Output Voltage VIN = 2.5 V, Single Supply Mode 1.71 1.8 1.89 V
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V 0.7 x VDDIO VDDIO + 0.3 V
2-Level Input (SCL, SDA), VDDIO = 2.5 V 0.7 x VDDIO 3.6
VIL Low Level Input Voltage 2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V -0.3 0.3 x VDDIO V
2-Level Input (SCL, SDA), VDDIO = 2.5 V 0 0.3 x VDDIO
VOH High Level Output Voltage IOH = -2 mA, (MISO), VDDIO = 2.5 V 0.8 x VDDIO VDDIO V
VOL Low Level Output Voltage IOL = 2 mA, (MISO), VDDIO = 2.5 V 0 0.2 x VDDIO V
IOL = 3 mA, (LOCK_N, SCL, SDA), VDDIO = 2.5 V 0 0.4
IIH Input High Leakage Current SPI Mode: LVCMOS (SS_N, SCK, MOSI), Vinput = VDDIO 15 µA
SMBus Mode: LVCMOS (LOCK_N, SCL, SDA), Vinput = VDDIO 10
IIL Input Low Leakage Current SPI: LVCMOS (SS_N), Vinput = VSS -40 µA
SPI: LVCMOS (SCK, MOSI), Vinput = VSS -15
SMBus: LVCMOS (CD_N, SCL, SDA), Vinput = VSS -10
4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
V4_LVL_H LEVEL-H Input Voltage Pull-up 1 kΩ to VDDIO VDDIO V
V4_LVL_F LEVEL-F Default Voltage Float, VDDIO = 2.5 V 2/3 x VDDIO V
V4_LVL_R LEVEL-R Input Voltage External Pull-down 20 kΩ to VSS, VDDIO = 2.5 V 1/3 x VDDIO V
V4_LVL_L LEVEL-L Input Voltage External Pull-down 1 kΩ to VSS 0 V
I4_LVL_IH Input High Leakage Current 4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL); Vinput = VDDIO 20 45 80 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VDDIO 20 45 80
I4_LVL_IL Input Low Leakage Current 4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VSS -160 -93 -40 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VSS -160 -93 -40
RECEIVER SPECIFICATIONS (IN1±)
RIN1_TERM DC Input Differential Termination Measured across IN1+ to IN1- 80 100 120 Ω
RLIN1_SDD11 Input Differential Return Loss (1) SDD11, 10 MHz - 2.8 GHz -21 dB
SDD11, 2.8 GHz - 6 GHz -17
SDD11, 6 GHz - 11.1 GHz -8
RLIN1_SCD11 Differential to common mode Conversion (1) SCD11, 10 MHz to 11.1 GHz -23 dB
VIN1_CM_TOL Input AC Common Mode Voltage Tolerance 15  mV (rms)
VIN1_CM DC Common Mode Voltage Input common mode voltage at IN1+ or IN1- to VSS 2.06 V
CDON_IN1 CD_N = LOW, Signal Detect (default), Assert ON Threshold Level 10.3125 Gbps, 1010 Clock Pattern 39 mVp-p
10.3125 Gbps, PRBS-31 Pattern 25
11.88 Gbps, EQ and PLL Pathological Pattern 20
CDOFF_IN1 CD_N = HIGH, Signal Detect (default), De-assert OFF Threshold Level for 10.3125 Gbps, 1010 Clock Pattern 15 mVp-p
10.3125 Gbps, PRBS-31 Pattern 15
11.88 Gbps, EQ and PLL Pathological Pattern 18
TRANSMITTER OUTPUT (OUT0± AND OUT1±)
VOD Output Differential Voltage(5) 8T pattern, VOD_DE = LEVEL-H, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE 		410 mVp-p
8T pattern, VOD_DE = LEVEL-F, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 485 560 620
8T pattern, VOD_DE = LEVEL-R, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 635
8T pattern, VOD_DE = LEVEL-L, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 810
VODDE De-emphasized Output Differential Voltage(5) 8T pattern, VOD_DE = LEVEL-H, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 410 mVp-p
8T pattern, VOD_DE = LEVEL-F, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 500
8T pattern, VOD_DE = LEVEL-R, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 480
8T pattern, VOD_DE = LEVEL-L, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE		 480
ROUT_TERM DC Output Differential Termination Measured across OUTn+ and OUTn- 80 100 120 Ω
tR/tF Output Rise/Fall Time(1) 20% - 80% using 8T Pattern SMPTE SD, HD, 3G, 6G, 12G, and 10 GbE, measured after 1 inch trace 45 ps
RLTX-SDD22 Output Differential Return Loss, Measured with the device powered up and outputs a 10 MHz clock signal.(1) SDD22, 10 MHz - 2.8 GHz -17 dB
SDD22, 2.8 GHz - 6 GHz -15
SDD22, 6 GHz - 11.1 GHz -15
RLTX-SCC22 Output Common Mode Return Loss, measured with the device powered up and outputs a 10 MHz clock signal.(2) SCC22, 10 MHz - 4.75 GHz -12 dB
SCC22, 4.75 GHz - 11.1 GHz -12
VTX_CM AC Common Mode Voltage(2) Default Setting, PRBS-31, 10.3125 Gbps 5 mV (rms)
OUTPUT JITTER
TJ Total Jitter (BER≤1e-12), Reclocked Output(4) 11.88 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.11 0.15 UI
5.94 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.106 UI
2.97 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.075 UI
1.485 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.07 UI
270 Mbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.07 UI
10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.09 0.15 UI
RJ Random Jitter, Reclocked Output 11.88 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 5 mUI (rms)
10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 4.1 mUI (rms)
DJ Deterministic Jitter, Reclocked Output 11.88 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 40 mUI
10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 34 mUI
TJRAW Total Jitter (BER≤1e-12), RAW (Reclocker Bypassed) 125 Mbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.17 UI
1.25 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± 0.17
CLOCK AND DATA RECOVERY
LOCKRATE Reclocker Lock Data Rates SMPTE 12G, /1 11.88 Gbps
SMPTE 12G, /1.001 11.868 Gbps
SMPTE 6G, /1 5.94 Gbps
SMPTE 6G, /1.001 5.934 Gbps
SMPTE 3G, /1 2.97 Gbps
SMPTE 3G, /1.001 2.967 Gbps
SMPTE HD, /1 1.485 Gbps
SMPTE HD, /1.001 1.4835 Gbps
SMPTE SD, /1 270 Mbps
10 GbE 10.3125 Gbps
BYPASSRATE Bypass reclocker data rate MADI 125 Mbps
1 GbE 1.25 Gbps
BWPLL PLL Bandwidth Measured with 0.2 UI SJ at -3 dB, 10.3125 Gbps 8 MHz
Measured with 0.2 UI SJ at -3 dB, 11.88 Gbps 13
Measured with 0.2 UI SJ at -3 dB, 5.94 Gbps 7
Measured with 0.2 UI SJ at -3 dB, 2.97 Gbps 5
Measured with 0.2 UI SJ at -3 dB, 1.485 Gbps 3
Measured with 0.2 UI SJ at -3 dB, 270 Mbps 1
JPEAKING PLL Jitter Peaking SD, HD, 3G, 6G, 12G, and 10 GbE 0.3 dB
JTOL_IN1 IN1 Input Jitter Tolerance per SFF-8431 Appendix D.11 Total jitter tolerance combination of Dj, Pj, and Rj at 10 GbE, with RX stress eye mask Y1, Y2 limits >0.7  UI
JTOL IN1 Input Jitter Tolerance with SJ Sinusoidal jitter, tested at 3G, 6G and 12G; SJ amplitude low to high sweep, tested at BER ≤ 1e-12 0.65 UI
TLOCK Reclocker lock time All supported data rates, disable HEO/VEO monitor 5 ms
TEMPLOCK VCO Lock with Temp Ramp Lock Temperature Range (5 °C per min, ramp up and down), -40°C to 85°C operating range  125 °C
TLATENCY Reclocker Latency(3) IN1, all supported data rates 1.5 UI + 190 ps
TPD-RAW Propagation Delay Raw Data (reclocker bypassed), IN1± EQ = default 190 ps
FCLKOUT Output Clock Frequency OUT1 Programmed to Output Recovered Clock Operating at 11.88 Gbps 297 MHz
Operating at 5.94 Gbps 297 MHz
Operating at 2.97 Gbps 2.97 GHz
Operating at 1.485 Gbps 1.485 GHz
Operating at 270 Mbps 270 MHz
(1) This parameter was measured with an LMH1219EVM.
(2) This parameter was measured with an LMH1219EVM.
(3) This parameter is data rate dependent. For example, at 11.88 Gbps, 1.5 UI = 1.5 x 84.17 ps = 126.25 ps. Therefore, TLatency = (126.25 + 190) ps = 316.25 ps.
(4) These limits are ensured by bench characterization and are not production tested.
(5) ATE production tested with DC method.